As a general display interface, VGA can use many devices. According to the document of VGA, we know that to use VGA, we only need to send different signals to the VGA cable at a given clock frequency.

There are five effective signals in VGA output

VGA_ Red (red terminal), VGA_ Blue, VGA_ Green (green terminal), VGA_ Hsync (horizontal synchronous terminal), VGA_ Vsync (vertical synchronous terminal).

If the horizontal scanning method is adopted and the resolution is 640 x 480, we need to:

The clock frequency is 25MHz (or 28.3mhz, refer to VGA document).

The output signal of horizontal synchronization terminal consists of four stages, each cycle takes up 800 clock cycles.

Pulse period (for synchronization): 96 cycles, output low level

Front end cycle (for buffering): 48 cycles, output high level

Display cycle (for display): 640 cycles, each clock cycle displays the content of a pixel, and reads the information of red, blue and green terminals for display. The synchronization terminal outputs high level.

Back end cycle (for buffering): 16 cycles, output high level

The output signal of vertical synchronization terminal also includes four stages. Because it is horizontal scanning, the horizontal synchronization terminal will display it correctly in the display cycle of vertical synchronization. It contains 480 horizontal synchronization cycles and scans 480 lines. It can also be said that in a vertical synchronization cycle, the contents of a screen are displayed.

The pulse period of vertical synchronization terminal is two horizontal synchronization periods; The back-end cycle is 29 horizontal synchronization cycles; The display cycle is 480 horizontal synchronous cycles; The front-end cycle is 10 horizontal synchronization cycles, so the total number of cycles is

[latex]T=(480+2+10+29) * (96+16+640+48) = 416800[/latex]cycles

Refresh rate is

[latex]f = frac {25MHz} {416800} = 59.98 Hz[/latex]

That is, the refresh rate of the screen is about 60Hz. If we need to use other resolutions, we only need to change the display cycle length and provide different clock cycles for the module. The display period and other parameters are in the VGA_ In the header. V file. In the process of writing, if the prompt on the screen is similar to “display out of range”, it means that the synchronization cycle is not correct. Correct the length of the synchronization cycle.

In order to realize the accurate timing of synchronous signal, we use finite state machine to control it. The following source codes are available for reference:

always @ (negedge clk)
begin
/* Vertical Sync. Signal */
case (v_state)
0:   begin        /* TPW synchronous pulse period*/
if (cv_thres == 0) begin
v_sync      <= 0; =””  =””  =””  =””  /*=””>=>
cv_ en        <= 0;  =””  =””  =””  =”” Counter continues to count = “> = >”
end else begin
v_state     <= 1; =””  =””  =””  =””>=>
cv_ en        <= 1;  =””  =””  =””  =”” Counter clear = “> = >”
cv_ value     <= ` vga_ sync_ v_ por_ back-1;  =””  =””  =””  =”” Counter set = “> = >”
v_ sync       <=  1;  =””  =””  =””  =”” Synchronization signal set high = “>”=  >
end
end
1: begin         /* TFP front end cycle*/
if (cv_thres == 0) begin
v_ sync                 <=  1;  =””  =””  =””  =”” Synchronization signal set high = “>”=  >
v_ addr                 <=  0;  =””  =””  =””  =”” Vertical address clear = “>”=  >
cv_en                <=  0; =””  =””  =””  =””>= >
end else begin
v_ state                 <=  2;  =””  =””  =””  =”” Enter the next state=  >
cv_ value         <=  ` vga_ sync_ v_ display-1;  =””  =””  =””  =”” Counter set = “>”=  >
cv_ en                 <=  1;  =””  =””  =””  =”” Counter clear = “>”=  >
v_ sync                 <=  1;  =””  =””  =””  =”” Vertical synchronization signal set high = “>”=  >
h_ state      <=  0;  =””  =””  =””  =”” Set horizontal synchronization status = “>”=  >
end
end
2: begin     /* Tdisp display cycle*/
if (cv_thres == 0) begin
v_ sync                 <= 1;  =””  =””  =””  =”” Vertical synchronization signal set high = “> = >”
cv_ en                 <= 0;  =””  =””  =””  =””  /*=”” Counter count = “> = >”
end else begin
v_ state                 <=  3;  =””  =””  =””  =””  /*=”” Enter the next state=  >
cv_ value         <=  ` vga_ sync_ v_ por_ front-1;=”” Counter set = “>”=  >
cv_ en                 <=  1;  =””  =””  =””  =”” Counter clear = “>”=  >
v_ sync                 <=  1;  =””  =””  =””  =”” Vertical synchronization signal set high = “>”=  >
end
end
3: begin         /* TBP back end cycle*/
if (cv_thres == 0) begin
v_ addr                 <=  0;  =””  =””  =””  =”” Vertical address clear = “>”=  >
v_ sync                 <=  1;  =””  =””  =””  =””  /*=”” Vertical synchronization signal set high = “>”=  >
cv_ en                  <=  0;  =””  =””  =””  =””  /*=”” Counter count = “>”=  >
end else begin
v_ state                 <=  0;  =””  =””  =””  =”” Enter the next state, i.e. state 0 = >=  >
cv_ value         <=  ` vga_ sync_ v_ pul_ width-1;=”” Counter set = “>”=  >
cv_ en                 <=  1;  =””  =””  =””  =””  /*=”” Counter clear = “>”=  >
v_ sync                 <=  0;  =””  =””  =””  =””  /*=”” Vertical synchronization signal set low = “>”=  >
end
end
endcase
/* …… *

After generating the horizontal and vertical synchronization signals and the corresponding horizontal and vertical addresses, the module uses the vertical and horizontal addresses to read the corresponding pixel information

a. Graphic mode: graphic mode is a pixel by pixel, we use blockram to save the pixel information. Due to the limited space, we can only save 320 x 240 pixels, and expand the output range to 640 x 480 monochrome output. Otherwise, the compilation will fail because of the lack of space. If we can use the built-in DDR module on the board, we can expand its scale. The DDR SDRAM on the board has 64M, which is a module produced by MgO. There are corresponding modules in the IPCore provided by Xilinx. We only need to provide the corresponding pins after the establishment to complete the output. Because the D / a module can’t do it (see below), this modification doesn’t make much sense, so we didn’t do it in this project.

b. Text mode: the text mode supports the display of 80 x 30 characters. We still use blockram to save these characters. Each character takes up 3 bytes to represent its ASCII code (1 b) and 16 bit RGB information (5-6-5 format, 2b). After the characters are displayed, the corresponding pixel information is generated through the textfontrom module of the font library. Read out the characters that should be displayed in a line, and then display them on the screen. Since the memory consumption is not as large as that of graphic mode, we use 640 x 480 format output.

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