In electronic systems, connectors used to connect circuit boards and modules are not only expensive, but also occupy valuable space of circuit boards and systems, and they also reduce the stability of products.

Lattice has developed an innovative method, which allows system architects and developers to use a very small low-power FPGA to greatly reduce the number of connectors between boards and modules, increasing system stability while reducing space occupation and cost.

Developers with FPGA design experience can also customize the solution. Even without FPGA design experience, developers can easily and quickly complete the deployment.

Optimize connectivity

The vast majority of today’s electronic systems contain two or more circuit boards and / or modules. (unless otherwise specified, the term “circuit board” or “board” below will include “module” by default.)

For system designers, the problem they often face is to connect circuit boards for data transmission. A common solution is to install the multi pin connector on the circuit board, and then use multiple wiring harness or wires to connect the circuit board together.

However, each connector pin is a potential failure point. Therefore, in addition to increasing cost and occupying space, connector is usually a key factor affecting the reliability of electronic system. This means that minimizing inter board connections can reduce costs, reduce space consumption and improve system stability.

Figure 1. Traditional connectors are not only expensive and take up space, but also reduce system stability

Designers of all kinds of systems – from handheld devices, laptops to industrial controllers – are eager to minimize the number of connector pins and wiring between circuit boards.

Single line aggregation: advantages of FPGA

The principle behind single wire aggregation (SWA) is to aggregate multiple signals into a time division multiplexing (TDM) signal, which only needs one cable to transmit between circuit boards. One way to implement this solution is to create custom application specific integrated circuits (ASICs) for each product (Figure 2).

Figure 2. Developing custom ASIC is expensive, time-consuming and inflexible

However, customized ASIC solutions have many disadvantages, such as high development cost and time-consuming. What’s worse, any algorithms and functions they contain are actually “frozen in the chip”, which means that they can’t adapt to changing needs. For example, the sales director suddenly announced: “our biggest customer said that we need to replace one of the I2S interfaces with two I2C channels.”

The ideal solution is to use low-cost field programmable gate array (FPGA), such as lattice semiconductor’s ice40 ultraplus Gamma Device (Figure 3).

Figure 3. FPGA is cheap and flexible

One of the great advantages of using FPGA to implement single line aggregation is that they are very flexible and can be customized quickly and easily to achieve the required number and type of channels.

FPGA designers use ice40ultraplus to realize single line aggregation

There is such a statement in the previous paragraph: “FPGA based single line aggregation can be customized quickly and easily.”. This sentence has a premise that you need to be very familiar with FPGA design.

If you are a FPGA designer, lattice can provide you with the easiest FPGA development tools in the industry. In addition, in the single line aggregation solution, lattice also provides a full set of reference design resources, together with its industry-leading ice40 ultraplus Gamma FPGA:

Easy to modify and parameterize source code of single line aggregation reference design, which can be run on radiant design tool of lattice

Free use of laticeradiant design tools

Relevant reference design User Guide

One line aggregation demonstration and development board

However, not all design teams have FPGA design experience. Fortunately, lattice also provides solutions for non FPGA designers.

Non FPGA designers use ice40ultraplus to realize single line aggregation

Take a system based on microcontroller (MC + + U) as an example. Some members of the design team can skillfully use C or C + + to develop software, and then run the software compiler, which generates executable files from machine code. Other members of the team only need to load the machine code file into the MCU, and do not need to know any programming related information.

Similarly, FPGA developers are specialized in using hardware description language (HDL) such as Verilog or VHDL to describe the design, and then run the hardware compiler called logic synthesis engine to generate the HDL configuration file, commonly known as bit stream. Other members of the team can load the bitstream into the FPGA without knowing anything about the FPGA design.

The first one line aggregation solution for non FPGA designers provides five pre synthesized bit streams (Figure 4). These configurations are the results of many practical applications and can meet the requirements of various system designs.

Figure 4. Provides a precompiled bitstream with five common configurations

Users can get one line aggregation solutions from the lattice website( -Cn / singlewire). The guide describes how to load a preconfigured bitstream into the ice40 ultraplus FPGA.

In addition, lattice also provides free one-line aggregation design services. You can visit lattice’s one line aggregation development board website( -Cn / products / development boards and kits / singlewire), fill in the form to specify the channel combination required by your design, and then the lattice design team will send you the corresponding bitstream file by e-mail.


In order to better illustrate the content of this paper, we need to briefly understand the devices that realize single line polymerization. Ice40 ultraplus FPGA has a flexible logic architecture, 2800 or 5280 4-input look-up tables (LUTS), customizable general purpose I / O (GPIO), up to 80Kb embedded memory block (EBM) and up to 1MB embedded SRAM.

Ice40 ultraplus FPGA can realize ultra-low power advanced processing function in most applications, with quiescent current as low as 75ua and working current as low as 1-10ma. In addition, ice40ultraplusfpga also provides a variety of packaging options to meet the needs of various applications

The 2.15×2.50mm ultra small WLCSP package is specially optimized for consumer electronics and Internet of things devices, and the 0.5mm pin spacing 7x7mm QFN package can meet the needs of cost optimized applications.

Since the configuration bit stream can be loaded directly into the SRAM based configuration unit, ice40 ultraplus FPGA can be reprogrammed repeatedly. In this way, designers can try to use different designs and bitstreams, which is the best choice in the prototype development phase of the project.

If the ice40 ultraplus device based on SRAM is used in the product, the configuration can be loaded through the on-board MCU or from the external SPI flash device.

In addition, ice40 ultraplus FPGA also contains one-time programmable (OTP) nonvolatile configuration memory (nvcm), which is very suitable for mass production. After programming the nvcm, the device will automatically, quickly and safely boot from this configuration.

Single line aggregation demonstration and development board

The SWA demo and development board contains two ice40 ultraplus FPGAs. One is used as data generator or data verifier, and the other is used to realize single line aggregation reference design (used as controller or peripheral).

Figure 5 shows the typical use scenarios of the two development boards. In this case, the development board on the left includes data generator and single line aggregation controller, while the development board on the right includes single line aggregation peripheral and data verifier.

Figure 5. One line aggregation demonstration and development board configuration block diagram

Observe the jumper in the figure. If these jumpers are retained, the data from the data generator on the left demonstration board will be fed to the one wire aggregation controller reference design, which aggregates them into a single signal for transmission to the right demonstration board. The single line aggregation peripheral reference design on the right demonstration board will receive the aggregation signal and feed the disaggregation signal to the data verifier. Figure 6 (a) shows this process.

Figure 6. Two application cases

Summary of features of one line aggregation solutions

As mentioned above, the one line aggregation reference design runs on two ice40 ultraplus FPGAs. One FPGA aggregates multiple data streams (such as I2C, I2S and GPIO) in time division multiplexing mode, and then sends them to another FPGA through one line to depolymerize the original data stream.

The single line communication speed between two FPGAs is about 7.5mbps. The design can also be configured by itself — the number of I2C / I2S bus and GPIO can be adjusted, and the length of one line protocol packet can be adjusted. The one line protocol between FPGAs has the function of error detection and retrial. A brief overview of the features of the solution is as follows:

· aggregate up to 7 channels

· the raw data rate on a single line is about 7.5mbps or higher

Variable packet length for efficient utilization of single line bandwidth

When the parity check error occurs at the receiving end, it can be retransmitted

Fast mode (400kbps) and fast mode plus (1Mbps) supporting I2C

The I2C interrupt can be implemented by GPIO and event based transmission

The I2S supports single stereo channel, 48Khz sampling rate, up to 32-bit sampling and bidirectional support


Many electronic systems today include multiple circuit boards. In addition, most of these systems use a variety of different types of interfaces (such as I2C, I2S and I2C)GPIO) collects data from peripherals and sensors and transmits it between circuit boards.

Transmitting signals on crowded circuit boards and connectors can cause many problems. In addition, the area of circuit boards and the internal space of the system are usually very valuable. In addition to increasing cost and space, connectors are usually the most unreliable components in a system.

Lattice has developed an innovative method for system architects and developers to use small-size, low-cost FPGA to achieve single line aggregation, significantly reducing the number of inter board connectors, improving system stability and reducing system size and cost.

Developers with FPGA design experience can customize the solution. In addition, even without any FPGA development experience, developers can quickly and easily complete the deployment.

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