Author: wofle Yu
With the advent of the era of big data, cloud computing and the Internet of things, the communication system has developed from a centralized system to a distributed system. In the centralized system, all processes or modules obtain time from the unique global clock of the system, and any two events in the system have a clear sequence relationship.
In a distributed system, the system cannot provide a unified global clock for independent modules. Because the timing rate and operating environment of these local clocks are inconsistent, these local clocks will also be inconsistent after a period of time. In order for these local clocks to reach the same time value again, time synchronization must be carried out.
Wolfe Yu, an engineer of Excelpoint Shijian, a technology-based authorized agent, explained the relevant knowledge of 5g communication clock synchronization.
Clock synchronization technology
For the synchronization of each clock in the system, it is necessary to compare the difference between each clock and the system standard clock, and correct the relative drift. For example, in the user equipment of GPS navigation system, we generally do clock synchronization by adjusting the appearance time of 1PPS signal front. Another is to synchronize the clock through the clock recovery technology of Ethernet, which is called synchronous Ethernet technology, or synce. Of course, there are other technologies, such as transmitting time information through radio waves, but these transmission methods can only realize the same frequency transmission.
In order to meet the requirements of higher accuracy, a PTP transmission mode is proposed. Later, with the continuous improvement of 5g technology, the combination of synce + PTP was proposed.
GPS clock synchronization
GPS synchronous 3D coordinate theory
GPS system uses the working satellite to determine the three-dimensional coordinates of the receiver and obtain the clock deviation of the receiver for time service. Theoretically, as long as four or more working satellites are received, they can be accurately positioned and timed through the spatial three-dimensional coordinate formula. The coordinate theory is shown in the figure below, and the specific derivation process is not repeated.
Principle of GPS high frequency synthesizer system
In 2004, Nicholls and Carleton proposed the famous n / C system. The core technology of the N / C system is to use 10MHz OCXO to connect a frequency divider and a frequency multiplier at the same time, generate 1PPS and 160MHz signals respectively, and use the phase-locked loop to correct the output frequency of OCXO in real time.
In order to facilitate intuitive analysis, we reconstruct the system. The GPS receiver generates 1PPS output signal, and the 10MHz frequency division output 1PPS signal generated by OCXO, and then detect the phase offset through the 10MHz frequency doubling 160MHz signal to realize synchronization.
The essence of synchronization is to adjust the frequency and phase through phase-locked loop. Digital phase-locked loop DPLL has strong tolerance to digital circuit noise, fast acquisition time, easy integration and can provide complex processing algorithms.
Digital phase locked loop mainly includes phase detector, digital loop filter, phase accumulator, DA conversion, etc. The phase discriminator compares the local estimated signal with the input signal to generate the corresponding phase error sequence. After loop filtering, the phase control word is generated to adjust the phase. At the same time, the frequency control word adjusts the frequency output.
At present, most PLLs adopt a structure based on DDS + PLL, which can quickly lock the phase and frequency by calculating the frequency control word and phase control word respectively.
Synce clock synchronization
Synce (synchronous Ethernet) architecture
Synchronous Ethernet technology is a technology that uses Ethernet link code stream to recover clock frequency, referred to as synce for short. It uses high-precision clock at the Ethernet source end, uses the existing Ethernet physical layer interface PHY to send data, and recovers and extracts the clock frequency through CDR at the receiving end to maintain high-precision clock performance. The synce technical block diagram is as follows:
Basic principle of CDR (clock data recovery)
The Ethernet PHY layer transmits the NRZ code stream. On the transmission side, the code stream is re encoded into 4B / 5b, 8B / 10B and 64b / 66b codes, and the clock and data recovery can be completed through CDR (clock data recovery).
The principle of CDR is roughly as follows: the frequency discrimination ring coarse loop completes frequency acquisition, and the phase discrimination ring fine loop adjusts the phase and restores the clock relationship to recover the data signal.
CDR circuit is mainly divided into:
- The double loop CDR consists of a phase-locked loop and a delay phase-locked loop. The phase-locked loop provides a low jitter quadrature clock with the required frequency, and the phase-locked loop adjusts the phase of the quadrature clock to the best sampling phase;
- Full digital CDR. This circuit adopts full digital circuit and is realized by oversampling method. The power consumption is low, but the accuracy is limited;
- There is also a CDR without reference clock. This circuit does not need to provide off-chip reference clock. It has flexible application, but the working frequency range is small.
Synce plays an excellent role in frequency tracking in clock synchronization, but synce cannot judge the transmission delay of clock signal on the line in clock transmission.
Evolution of precision time protocol (PTP)
Network time synchronization protocol (NTP) theory
PTP evolved from NTP. Let’s talk about the NTP network protocol first. Send a message packet from the clock to the master clock and record the slave timestamp T1 of the message packet. The master clock immediately records the master timestamp T2 after receiving the message packet. At the same time, the master clock returns a message packet with the master timestamp T3 to the slave clock. After receiving the returned message packet from the clock, Immediately record the timestamp T4 from the clock.
At the same time, we assume that the two-way path is symmetrical, that is, the time from master to slave or from master to master is the same. Based on the above, we can easily get the transmission time of two-way path.
Disadvantages: pure software computing time requires organization of message transmission and multiple calibration. Message transmission may be asymmetric and delayed, so the accuracy is not high.
Precise time protocol (PTP) theory
IEEE 1588 PTP protocol is optimized based on NTP protocol. In hardware, each network node must have a network interface card containing real-time clock to meet the time stamp requirements.
IEEE 1588 network clock is mainly divided into ordinary clock OC (ordinary clock) and boundary clock BC (boundary clock). The clock of only one PTP communication port is ordinary clock, the clock of multiple PTP communication ports is boundary clock, and each PTP port communicates independently. Theoretically, we first determine an optimal clock as the master clock of the network. PTP marks the master-slave clock timestamp through the timestamp unit (TSU). The TSU monitors the input and output data stream at the same time. When the preamble of IEEE 1588 PTP packet is recognized, a timestamp is issued to accurately mark the arrival or departure time of PTP time packet.
PTP protocol is based on pure software synchronous data packet transmission. PTP communication message is mainly divided into synchronization message sync and follow message follow_ Up (Note: follow_up message is not required, and some modes are not required, such as one-step mode), delay the request message delay_ Req, delayed response message delay_ Resp and management message.
IEEE 1588 PTP protocol time deviation correction:
- The master clock sends a sync message to the slave clock and records the sending time TM1. At the same time, start the timer. After receiving the message from the slave clock, record the receiving time TS1;
- The master clock then sends a follow with TM1_ Up message;
- Calculate the offset time offset through the above two pieces of information;
- The interval master clock sends the second sync message to the slave clock and records the sending time TM2. After receiving the message from the slave clock, record the receiving time TS2;
- The master clock then sends a follow with TM2_ Up message;
- The TS time is corrected by the above offset time offset.
Based on the above steps, the corrected TS time is consistent with the TM time.
IEEE 1588 PTP protocol delay calculation:
- The master clock sends a sync message to the slave clock and records the sending time T1. After receiving the message from the slave clock, record the receiving time T2;
- The master clock then sends follow with T1_ Up message;
- Send delay from clock to master clock_ Req message is used to initiate the calculation of reverse transmission delay and record the sending time T3. After receiving the message, the master clock records the receiving time T4;
- Master clock received delay_ After the req message, reply to a delay with T4_ Resp message.
Based on the above four timestamps, each time delay can be calculated.
Synce + PTP theory
The most basic application premise of IEEE 1588 PTP synchronization is that it must be based on the strict consistency of uplink and downlink clock frequencies. If the uplink and downlink clocks are not constant, the accuracy of time synchronization will be greatly reduced.
Using synce, the slave device obtains the master clock frequency through Ethernet, recovers the accurate clock frequency, and assists PTP to achieve phase alignment and time synchronization.
Wolfe Yu, engineer of Excelpoint Shijian, introduced that microchip represented by Shijian has a complete clock solution provider with a history of nearly 60 years, such as Zarlink, Maxim timing & sync Bu, Micrel, Vectron, Vitesse, Actel, etc., which can provide users with turnkey solutions.
SyncE & IEEE 1588
Microchip has a variety of time solutions, including GPS, synce and IEEE1588 hybrid centralized systems and precise time systems, which can meet the product needs of different combinations of high, medium and low grades.
Main features of zl30735
Up to 5 independent channels DPLL;
3-way NCO, separate XO, standby clock mode hybrid channel DPLL;
Multichannel frac_ N output divider;
Each channel supports any frequency conversion;
Up to 10 channel differential or single ended input, 10 channel differential or 20 channel CMOS output;
Meet ITU-T g.8262, g.8262.1, g.813, g.812, Telcordia gr-1244, gr-253;
Meet ITU-T g.8261, g.8263, g.8273.2 (Class A, B, C, d), g.8273.4;
Jitter performance is less than 150 fs RMS.
Constant temperature crystal oscillator (OCXO) for short is an oven controlled crystal oscillator, which uses a constant temperature bath to keep the temperature of the quartz crystal resonator in the crystal oscillator constant. OCXO is composed of thermostatic bath control circuit and oscillator circuit. Usually, people use differential series amplifier composed of thermistor “bridge” to realize temperature control.
Microchip has launched a variety of ocxos for customers to choose from, with output frequency up to 3GHz, temperature stability up to 0.15ppb and aging rate up to 20ppb.
Voltage controlled oscillator refers to an oscillation circuit (VCO) whose output frequency corresponds to the input control voltage. The frequency is an oscillator VCO as a function of the input signal voltage. The working state of the oscillator or the component parameters of the oscillation circuit are controlled by the input control voltage to form a voltage controlled oscillator.
Microchip VCXO selection list：
In addition, Excelpoint Shijian can provide a complete set of turnkey solutions based on microchip integrated IEEE1588, synce PHY chip and IP protocol package, help 5g small base stations Du, Ru and hub, and shorten customer development cycle.