With the development of social economy and the improvement of living material level, people’s pursuit of the spiritual world is also higher and higher. The design concept comes from improving people’s life happiness index. In the traditional sense, people often use the developed photos to record the beautiful moments in life. However, with the development of the electronic industry, including digital cameras, a large number of high-pixel intelligent electronic products are popular enough to replace them with digital form. According to statistics, more than 70% of the photos in the world are digital photos, and young people like to record their lives in digital form and share them on the Internet. At the same time, digital photo frame can also upgrade static pictures to dynamic photo albums, which is easy to carry, long-term storage time, and meets people’s needs. At the same time, it will also be an energy-saving, environmental protection and low-carbon concept.
Working principle of FPGA
A typical FPGA is composed of several parts, the first is logic block, which is called logic array fast (Lab) by Altera company and configurable logic block (CLB) by Xilinx company. Lab consists of basic units called Le (logic element), and CLB consists of basic units called LC (logic cell). These are the logic resources of FPGA, and some of them are the internal wires scattered among the logic blocks. They are like the wires on the PCB board, which connect the internal logic of FPGA. The starting point and the ending point are iob (I / O block). The other part is iob. Iob is the external physical interface of FPGA, which is similar to the pins of IC. Of course, it can be defined according to the user’s needs. Nowadays, the iob of FPGA is very powerful. From the basic LVTTL / lvcoms interface to PCI / LVDS / RSDS and even various differential interfaces, the internal I / O of FPGA is actually grouped, but each group can be flexibly configured to change the pull-up and pull-down resistance and adjust the driving current. It can also accommodate 5V, 3.3V, 2.5V, 1.8V and even 1.5V, which can meet different electrical characteristics and different I / O requirements The physical characteristics of the interface and various matching requirements of the external hardware circuit for the input and output signals. At present, the frequency of I / O is getting higher and higher, and the data reading rate can even reach 2gbps through specific technology. Now more and more engineers like FPGA, and the powerful I / O characteristics are also a reason.
Figure 2-1 typical internal structure of FPGA
I / O compatibility is the trend of the times. There are still many concepts and techniques for designing iob, which will not be introduced here. Another part is the internal function module of FPGA, which is placed in FPGA by the manufacturer according to the actual needs. For example, digital clock management module (DCM) and Xilinx FPGA all have this function. For example, phase loop locking. PLL needs an external clock input (crystal oscillator). After internal processing (including frequency division and frequency multiplication), PLL can provide a stable clock in a certain range of frequency and phase. There is also a block ram that does not occupy logic resources. Ram block can be used as single port RAM, dual port RAM, content address memory, FIFO (first in first out) and other common memory, even ROM, shift register. This is very useful for a small amount of data cache and enhances the applicability of FPGA. When choosing FPGA, the amount of ram resources in the chip is also an important factor. The capacity of a single block ram is 18kbit, the width is 18bit, and the depth is 1024. The bit width and depth can be changed according to the actual needs, but there are two limitations: first, the capacity of the modified block RAM (bit width and depth) can not be greater than that of a single block ram; and the maximum bit width can not exceed 36bit, and the multi block RAM can be changed At this time, it is only limited by the number of ram blocks in the chip, and is no longer constrained by the above two principles. However, in quartus, the specific operation is very convenient. There are also low-level embedded functional units, including embedded dedicated hard core such as multiplier. It provides great convenience for the operation and processing of digital signals.
SPI interface control circuit
Figure 4-1 SPI mode connection diagram
The four signal lines of SPI interface of the project module are SPI_ cs_ n，spi_ clk，spi_ Miso and SPI_ mosi。 Among them, SPI_ cs_ N is the data control enable signal. When the chip is to be operated, the low level of the signal is valid. That is to say, multiple SPIs can be connected on the same main line. spi_ CLK is the SPI synchronous clock signal, and the data signal is transmitted bit by bit under the control of the clock. spi_ Miso and SPI_ Mosi is the data signal of master-slave communication, SPI_ Miso is the input of the host or the output spi of the slave_ Mosi is the output of the host or the input of the slave.