LED has been widely used in lighting, backlight and other fields because of its low power consumption, high luminous efficiency and long service life. The brightness of LED is directly proportional to the working current. In order to maintain the stability of brightness, a stable constant current power supply is needed. In terms of power management, DC / DC converter has the advantages of small volume, low power consumption, high efficiency and convenient use, so it is widely used. The LED driving circuit based on DC / DC boost converter has also become a classic LED driving mode. DC / DC converters have many control modes, among which peak current mode is widely used in industry because of its fast response speed. However, when the duty cycle is greater than 50%, the circuit is prone to subharmonic oscillation, which needs to be eliminated by introducing slope compensation circuit.
2 circuit design and analysis
Figure 1 shows the LED driving circuit designed in this paper, which is composed of four parts: slope signal generation circuit, current sampling and superposition circuit, error amplifier and PWM comparator.
Fig. 1 LED driving circuit based on DC / DC converter
2.1 ramp signal generation circuit
Fig. 2 shows a ramp signal generation circuit, in which OP is a clamped operational amplifier. It can be seen that the reference voltage Vref acts on the adjustable resistance RL after being divided by resistors R10 and R11, and then clamped by the voltage of the operational amplifier to produce a constant current. After the current passes through the mirror image of the four MOS transistors MP1 ~ MP4, it becomes a constant current signal for charging the capacitor. It can be calculated from the circuit structure that the current is:
Since the reference voltage is a constant voltage, the resistors R10 and R11 match each other, and the resistance RL is an approximate zero temperature resistance formed by the polycrystalline resistance with positive temperature coefficient and the well resistance with negative temperature coefficient in series, this current is approximately a reference current. When the current acts on the capacitor, the sawtooth wave voltage signal can be generated by controlling the charge and discharge of the capacitor through the square wave signal, and the slope M0 of the sawtooth wave is:
After the sawtooth voltage is raised by veb1, it is input to the signal superposition module. The vslope terminal voltage is a sawtooth voltage. Therefore, in Figure 2, the current mirror adopts a self bias structure. Compared with ordinary cascode current mirror, this current mirror has larger output voltage swing and can meet the requirements of wide voltage variation range at vslope terminal.
Fig. 2 ramp signal generation circuit.
Sampling current and superposition circuit
Compared with voltage mode, current mode has faster transient response speed. However, when the duty cycle is greater than 50%, the circuit is prone to subharmonic oscillation, which needs to be overcome by adding an additional slope compensation circuit.
In this paper, the compensation method of superposition of the output signal of sampling circuit and slope compensation signal is adopted.
The current sampling and superposition circuit is shown in Figure 3. The current sampling circuit is actually a two-stage operational amplifier, Mn3 and Mn4 are the first stages of the operational amplifier, which form a common grid differential pair structure, and the current mirrors mp14 and MP15 are used as active loads. Mn5 is the second stage of the operational amplifier, a common source structure, and MP12 is used as the active load.
Fig. 3 current sampling and superposition circuit.
MP1 is used to provide a quiescent current for the second stage, so that when CS terminal is zero, the second stage can still have a quiescent current to keep the second stage open. The specific principle is: if the dimensions of mp14 and MP15 are the same, the currents i5 and I6 are equal; Meanwhile, Mn3 and Mn4 have the same size, and their gate source voltage should also be the same. As can be seen from Fig. 3, the gate potentials of Mn3 and Mn4 are the same, which determines that their source voltages should also be the same, that is, the voltage drop on resistors R4 and R5 is the same, so that currents i7 and I8 are equal. Since i7 = I4 + i5, I8 = I3 + I6, combined with the previous analysis i5 = I6, I3 = I4 can be obtained. According to the above analysis, the current of the second stage of the operational amplifier is set by mp13, and the static current of the second stage is adjusted by changing the current mirror ratio of mp13 and MP16.
When the CS terminal has a value of VCs, the output of the first stage of the operational amplifier should be increased, so as to increase the current I3. The specific analysis is that if the size of I4 and i5 is constant, the voltage drop on resistor R4 is constant. After the voltage at CS terminal increases VCs, the voltage on R4 also increases VCs, and the voltage on R5 should also increase VCs. This requires that the current on R5 increase VCs / R5. Since I6 remains unchanged, I3 should increase VCs / R5. VCs is the voltage drop caused by inductive current acting on a small sampling resistor, The change of VCs reflects the change of inductance current, and the change of VCs is completely proportional to the change of inductance current. Assuming that the sampling resistance is RS and the slope of inductive current is k, the slope of I3 is KRS / R5. Let the rising slope and falling slope of inductive current be K1 and K2 respectively, and the corresponding slopes of I3 are k1rs / R5 and k2rs / R5 respectively. The current superposition module is composed of MP10, MP11, R3 and Q3. As can be seen from Fig. 2, vslope is one VBE higher than the voltage on capacitor C1, and in Fig. 3, another VBE decreases and acts on R2, which is equivalent to that the voltage on capacitor C1 acts directly on resistor R2. In combination with equation (2), the slope M1 of current I2 is:
The current acts on the resistor R3 through the mirror image to obtain the compensated slope m:
The current on MP11 is the sampling amplification current of the sampling circuit. This current acts on the resistance R3 to obtain the slope m ‘of this voltage:
The falling slope of inductive current is converted into:
It can be seen from references  ~  that in order to ensure that the circuit does not have subharmonic oscillation, M > 1 / 2m ′ 2 should be made, that is:
After the compensated signal rises VBE through Q3, ramp signal is generated and input to PWM for comparison with the output of error amplifier.
2.3 error amplifier
The function of the error amplifier is to sample the feedback voltage, output a control signal, and then input it into the PWM comparator to control the peak value of the current. When the LED works, due to the process deviation, the forward voltage drop on each LED will not be the same, so the voltage at each LED voltage sampling point will not be the same. In order to ensure that each LED can work normally, the circuit shall input the signal with the lowest sampling voltage into the error amplifier and compare it with the reference voltage. In this paper, the error amplifier has self selection function, and the circuit structure is shown in Fig. 4.
Figure 4 error amplifier.
Since the input pair is PMOS, the bias current will flow to the channel with the lowest gate voltage, and the other three channels with relatively high gate voltage will be turned off to ensure that only one transistor is working at the inverting input end of the error amplifier when the circuit works normally.
As can be seen from Fig. 4, the circuit is a single-stage folded cascode structure, which has high output resistance and ensures the high voltage gain of the circuit. Combined with the basic knowledge of analog integrated circuit, the static gain of the circuit can be obtained:
Where GM is the transconductance of the input differential pair tube, / / represents the parallel resistance, gm14 and gm35 are the transconductance of transistors mn14 and mp35 respectively, and RO1, ro14, ro35 and ro30 are the output resistance of the differential input pair tube and mn14, mp35 and mp30 respectively.
The error amplifier in this paper has only one main pole. At the output end of the amplifier, it is related to the resistance and capacitance of the output end. Its size is expressed by P:
Where, C is the capacitance of the output terminal, which is mainly the transistor parasitic capacitance in the open-loop state.
2.4 PWM comparator
The PWM comparator compares the current sampling signal after slope compensation with the control signal output by the error amplifier. When the peak signal output by the current sampling circuit reaches the value of the control signal, the PWM signal reverses and generates a very narrow pulse signal to trigger the power tube off. The PWM comparator designed in this paper is shown in Figure 5. Compared with the ordinary comparator, there is one more transistor mp47 on the left side of the differential pair
Figure 5 PWM comparator.
When the circuit is started, because the output voltage of the system is very low, the output signal of the error amplifier will be very high, resulting in the duty cycle of the gate drive signal reaching 100%, resulting in a high pulse in the DC / DC output. After adding the SS terminal, the voltage signal at the SS terminal will rise slowly during startup, shielding the high VEA control signal, so that the duty cycle of the gate drive signal will rise slowly to realize the soft start of the circuit. When the soft start is successful, the voltage at SS terminal will also rise higher than VEA, so as to turn off mp47 and the circuit enters the normal working state.
3 simulation results and analysis
3.1 gain and phase curve of error amplifier
Fig. 6 shows the gain and phase curves of the error amplifier, where gain and phase represent the gain and phase of the error amplifier in the open-loop state respectively. As can be seen from the figure, in the open-loop state, the static gain of the error amplifier can reach 70dB, and the 3dB bandwidth can reach more than 10kHz; It can also be seen that the circuit has only one main pole, so there can be a 90 ° phase margin.
Figure 6 gain and phase of error amplifier.
3.2 functional simulation of the whole circuit
Fig. 7 shows the functional simulation results of the overall circuit. In the figure, OSC, slope, CS, VEA, ramp and PWM respectively represent oscillator output signal, ramp signal, current sampling signal, error amplifier output signal, output signal after superposition of sampling circuit output and ramp signal, and output signal of PWM comparator.
Fig. 7 overall circuit function simulation results.
As can be seen from Fig. 7, the ramp signal generation circuit outputs a fixed slope sawtooth signal slope under the control of the oscillator signal, which is superimposed with the signal output by the current sampling circuit to generate a ramp signal. When the circuit is stable, the output of the error amplifier is a constant value. When the power tube is turned on, the inductance current continues to increase, the sampling current at CS terminal increases synchronously, and the ramp signal also increases synchronously. When the value of ramp signal reaches VEA, the PWM comparator will flip, output a pulse signal and turn off the power tube.
Then, the inductance current begins to drop, and the sampling point current disappears until the next working cycle, and the clock signal output by the oscillator turns on the power tube again.
This paper designs an LED driving circuit based on DC / DC converter, including inductive current sampling circuit, slope signal generation circuit, error amplifier and PWM comparator. The sampling circuit amplifies the current signal on the sampling inductor and superimposes it with the slope compensation signal, then outputs it to the PWM comparator, and outputs a voltage pulse under the control of the output signal of the error amplifier to control the turn off of the power tube.
The slope compensation adopts the up slope compensation mode, and the circuit structure is simple and easy to implement. The error amplifier has the function of automatic signal selection without adding a selector, which can greatly reduce the power consumption and layout area.
Responsible editor; zl