What causes the edge of the signal waveform to return?

In the process of signal transmission, the impedance discontinuity will produce reflection. When the reflection signal is superimposed on the high or low level of the working level, it is easy to produce overshoot or ringing. When the reflection signal is superimposed on the edge of the waveform, it is easy to produce return channel or step. The return channel of clock signal has the risk of false triggering, while the return channel of common signal will reduce the bandwidth of signal. Therefore, to avoid the return channel, it is essential to ensure the continuity of the path impedance felt by the signal.

(the following contents are selected from the answers of some netizens)

The first thing to think about is the discontinuity of impedance and the existence of mutation point. It may be due to the improper use of the topology and the poor selection of the termination scheme, but we can not ignore the test factors, such as the selection of the test point, and even the sampling rate of the oscilloscope.

@Pole

Score: 3

The impedance is not well controlled to complete the trench. DDR2 particles and DDR3 particles (except the last one) are the most common

@Ouyang

Score: 3

The paper points out that the impedance mismatch between the test point and die leads to reflection, which leads to the return of the signal. The reflected signals are strung up and down the line, and when they meet with the normal signals, they hook up. The position of superposition determines the shape of the final waveform. 1. Due to the short circuit of the package in the chip, the reflected voltage and action time are small and short. When meeting in the range of level change, it will be superimposed on the rising edge to form a tick back. 2. When the reflection action time is long, the voltage corresponding to the rise time point will be raised during superposition, and the waveform without this reflection will be compared from the time axis, as if the signal arrived ahead of time. This magic phenomenon will be seen when crosstalk occurs, so crosstalk will not produce a backtick to the signal.

@South of the Yangtze River

Score: 3

The edge of the signal waveform is usually caused by reflection. The specific reasons include impedance mismatch, branching and so on.

@Surge

Score: 3

The second is the inaccurate selection of test points, and the other is to check whether the power supply is not monotonous

@moody

Score: 3

There are many reasons for the appearance of signal return channel (i.e. the non monotonicity of waveform edge), some of which are the impedance discontinuity, some of which are the observation points not in the right place, and some of which are the problems of topology. Or other, specific analysis of specific problems and with the help of simulation means to analyze.

@Long fengchengxiang

Score: 3

If the first floor is changed to 0 Ω, will the overshoot of the falling edge increase? The problem may be caused by insufficient driving capacity or too heavy load. You can consider terminal connection.

In fact, there are only a few cases of the generation of back ditch



1. Crosstalk causes return channel under specific conditions

2. Stub problem, high speed should be considered

3. The most common problem is that the test point is not at the end of the whole network (including multiple loads). The chip package routing usually has a delay of 50 to 350 PS

4. Impedance mismatch will cause overshoot and ringing, and the most common phenomenon is return ditch.

5. Too much load or too long link, insufficient driving capacity or too heavy load will also cause.

6. Improper termination position and use may lead to trench return.



The key point is the position of the return channel. Even if it is not at the voltage judgment threshold, the edge time will be prolonged, which will affect the time of rising edge or falling edge, thus affecting the bandwidth.

@Understand

Score: 3

The topological structure of DDR routing determines the termination position. Flyby mode is pulled up at the end of the link, and T-type routing is pulled up at the first branch. The matching resistance is equivalent to the line impedance, generally between 3050 ohm.

@Ben

Score: 3

1. Unmatched reflection 2. Insufficient driver 3. DDR reflection of FPGA in the case, which may be due to other reasons

@Blood boy

Score: 3

There are many factors that cause the back hook. It’s still necessary to analyze the point where the impedance of the device is discontinuous. The probe point on the signal line is one of the reasons why the oscilloscope test has back hook. The simulation has back hook, which should be caused by the contact point between the package and PCB. The lead in the package is also the point where the impedance is discontinuous.

@Gu Chengyun

Score: 3

There are risks in impedance discontinuities, such as through holes (especially mechanical holes), magnetic beads, connectors, packaging, etc.

@Zhang Tongtong

Score: 3

It should be caused by the reflection of stub caused by the impedance discontinuity at the test point

@Alan

Score: 3

40MTCXO output is as like as two peas in 10pF, and the same hook is replaced by 0 euro. The essence is to cause mismatch and reflection

@eletan

Score: 3

The clock has a return slot, but it’s OK?!

The source of the article: official account of WeChat: Mr. speed. Welcome to add attention! Please indicate the source of the article.

Leave a Reply

Your email address will not be published. Required fields are marked *