Author: bradhall, ADI

With the increasing demand of global connectivity, many Satcom systems are increasingly using Ka band, and the demand for data rate is also increasing. At present, the high-performance signal chain can support several thousand megabytes of instantaneous bandwidth, and there may be hundreds of transceivers in a system. The ultra-high throughput data rate has become a reality.

In addition, many systems have begun to shift from mechanically positioned static parabolic antennas to active phased array antennas. With the promotion of enhanced technology and higher integration, the size of components has been greatly reduced, which can meet the needs of Ka band. By forming zero position in the antenna pattern along the direction of interference signal, phased array technology can also improve the performance of interference reduction.

The following will briefly describe some tradeoffs in existing transceiver architectures and the applicability of different types of architectures in different types of systems. This analysis will decompose and introduce some key technical specifications of satellite system, and how to obtain the specifications of each component of transceiver signal chain layer from these system level technical specifications.

Decompose technical specifications from system level analysis

From the macro level, satellite communication system needs to maintain a certain carrier to noise ratio (CNR), which is the result of link budget calculation. Maintaining the CNR can guarantee a certain bit error rate (BER). The CNR required depends on many factors, such as error correction, information coding, bandwidth and modulation type. After determining the CNR requirements, the technical specifications of each receiver and transmitter can be obtained according to the requirements of high-level system. Generally, the first results are the gain system noise temperature (g / T) quality factor of the transceiver and the effective omnidirectional radiation power (EIRP) of the transmitter.

For the receiver, to get the low-level receiver signal chain specification from g / T, the system designer needs to know the antenna gain and system noise temperature, which is a function of antenna pointing and receiver noise temperature, as shown in equation 1. Based on this, the receiver temperature can be obtained by equation 2.


The noise figure of the receiver signal chain can then be calculated using equation 3:


After the receiver noise figure is known, cascading analysis can be carried out to ensure whether the signal chain meets the requirements of these necessary technical specifications and whether it needs to be adjusted.

For the receiver, the required EIRP is first determined based on the receiver’s distance (ground to satellite or satellite to ground distance) and receiver sensitivity. After the EIRP requirements are known, it is necessary to make a compromise between the output power of the transmit signal chain and the antenna gain. For high gain antennas, the power consumption and size of the transmitter can be reduced, but the cost is to increase the antenna size. EIRP is calculated by equation 4.


As long as the components used in the signal chain are carefully selected, the output power can be maintained and other important parameters can not be reduced, such as interference with the output noise and out of band RF energy of other systems.

Other important technical specifications of transmitters and receivers include:

·Instantaneous bandwidth: the spectrum bandwidth that can be digitized at any point in time

·Power processing: the maximum signal power to be processed by a signal chain without causing performance degradation

·Phase coherence between channels: for the emerging beamforming system, ensuring the predictability of phase between channels can simplify the processing and calibration of beamforming signals

·Spurious performance: ensure that the receiver and transmitter will not generate RF energy at an unexpected frequency, so as not to affect the performance of the system or other systems


Figure 1. Architecture comparison: (a) high and medium frequency (integrated TRX), (b) dual frequency superheterodyne architecture (with gspsadc)

(c) Single frequency superheterodyne architecture (with gspsadc), (d) direct frequency conversion (with I / Q mixer)

In the design process of signal chain, it is necessary to keep these and other technical specifications in mind, so as to ensure the design of a high-performance system that can meet the requirements of any given application, whether it is a broadband multi carrier aggregation hub or a single narrowband handheld satellite communication terminal.

Common architecture comparison

After determining the high-level technical specifications, we can decide which signal chain architecture to adopt. One of the key technical specifications listed above that may have a significant impact on the architecture is instantaneous bandwidth. This specification affects the receiver’s analog-to-digital converter (ADC) and the transmitter’s digital to analog converter (DAC). In order to achieve high instantaneous bandwidth, it is necessary to sample the data converter at a higher rate. The result will generally increase the power consumption of the whole signal chain. However, in terms of unit power consumption (w / GHz), it will reduce the power consumption.

For systems with less than 100 MHz bandwidth, it is best to adopt an infrastructure similar to figure 1a in many cases. The architecture combines the standard down conversion stage with the integrated direct conversion transceiver chip. The integrated transceiver can achieve ultra-high integration, thus greatly reducing the size and power consumption.

In order to achieve 1.5GHz bandwidth, the classic dual frequency superheterodyne architecture can be combined with the most advanced ADC technology, as shown in Figure 1b. This is a mature high-performance architecture, and the integrated frequency converter is used to filter out useless spurious signals. According to the received frequency band, a down conversion stage is used to convert the received signal into intermediate frequency (if), and then another down conversion stage is used to convert the final IF signal into low frequency signal that can be digitized by ADC. The lower the final if, the higher the ADC performance, but the cost is that it will increase the filtering requirements. Generally, due to the increasing number of components, this architecture has the largest size and the highest power consumption among the four options proposed in this paper.

Similar options are shown in Figure 1C, where a single frequency conversion stage is used to convert the signal to high if, which is then sampled by gspsadc. The architecture takes advantage of the more RF bandwidth that ADC can digitize and hardly leads to performance degradation. The latest gspsadc on the market can directly sample up to 9ghz RF frequency. In this option, if center is between 4GHz and 5GHz, which can achieve the best balance between signal link filtering requirements and ADC requirements.

The last option is shown in Figure 1D. The instantaneous bandwidth increase of this architecture is even greater, but its cost is very complex and may lead to performance degradation. This is a direct conversion architecture, using a passive I / Q mixer, which can output two if offset by 90 ° on baseband. Then a dual channel gspsadc is used to digitize the I and Q channels. In this case, up to 3GHz instantaneous bandwidth can be obtained. The main challenge of this option is to maintain quadrature balance between I and Q paths as the signal propagates through mixers, low-pass filters, and ADC drivers. Depending on the specific CNR requirements, this compromise may be acceptable.

The above briefly introduces the working principle of these receiver architectures from the macro level. The list doesn’t cover all the cases. You can also use a combination of various options. Although the comparison does not involve the transmission signal chain, each option in Figure 1 has a corresponding transmission signal chain, and the tradeoff is similar.

Example of Ka band satellite communication receiver

The advantages and disadvantages of various architectures are discussed above. Next, we can apply these knowledge to real signal chain examples. At present, many satellite communication systems operate in Ka band to reduce antenna size and improve data rate. This is particularly important in high throughput satellite systems. The following are examples of different architectures, which we will compare in more detail.

For systems requiring instantaneous bandwidth below 100MHz, such as very small aperture terminal (VSAT), high and medium frequency architecture (ad9371) with integrated transceiver chip can be adopted, as shown in Figure 2. The design can achieve low noise figure, and because of its high integration, its design size is the smallest. Its performance is summarized in Table 1.


Figure 2. High and medium frequency (integrated TRX), bandwidth up to 100MHz

As a hub for multiple users in satellite communication systems, these systems may have to process multiple carrier signals at the same time. In this case, the bandwidth or bandwidth / power of each receiver becomes very important. The signal chain shown in Figure 3 uses a high-speed ADC, ad9208, which is a recently released high sampling rate ADC and can digitize up to 1.5GHz instantaneous bandwidth. In this case, the if is set at 4.5ghz to achieve 1GHz instantaneous bandwidth. The bandwidth available here depends on the filtering requirements of the anti aliasing filter located before the ADC, but it is generally limited to ~ 75% of the Nyquist region (half of the sampling rate).


Figure 3. Single down conversion to high if with gspsadc

In systems requiring the highest instantaneous bandwidth and possibly at the expense of CNR, the signal chain shown in Fig. 4 can be used. An I / Q mixer, hmc8191 hmc8191, is used in the signal chain, and its image rejection performance is ~ 25dBc. In this case, the image rejection performance is limited by the amplitude and phase balance between I and Q output channels. This is the limiting factor of the signal chain without more advanced quadrature error correction (QEC) technology. The performance of the signal chain is summarized in Table 1. It should be noted that the performance of NF and IP3 is similar to other options, but the power / GHz index is the lowest among them, and the size of NF and IP3 is also the best in terms of the amount of bandwidth available at any time.


Figure 4. Direct conversion with I / Q mixer and gspsadc.

The three receiving options given here are shown in the following table, but it should be noted that the table does not list all possible options. The summary here aims to show the differences between the various signal chain options. In any given system, the final optimal signal chain may be either one of the three or a combination of any options.


In addition, although only the receiver side is shown in the table, there is a similar compromise in the transmitter signal chain. Generally, when the system changes from superheterodyne architecture to direct conversion architecture, it needs to make a trade-off between bandwidth and performance.

data interface

After the data is digitized by ADC or transceiver, it must be handed over to the system for processing through digital interface. All the data converters mentioned here adopt the high-speed jesd204b standard. They receive signals from the data converter, then pack the signals into frames, and then transmit them through a small number of wires. The data rate of the chip varies with the system requirements, but all the devices mentioned here have digital functions for decimation and frequency conversion, which can adapt to different data rates to meet different system requirements. The specification can support up to 12.5gsps on jesd204b channel, which is fully utilized by high bandwidth system transmitting large amount of data. For a detailed description of these interfaces, refer to the data book of ad9208 and ad9371. In addition, the choice of FPGA must consider the interface. Many FPGAs provided by suppliers such as Xilinx and Altera have integrated the standard in their devices, which provides convenience for integration with these data converters.


In this paper, various tradeoffs are introduced in detail, and some examples are given for the signal chain of Ka band satellite communication system. Several architecture options are also introduced, including the high and medium frequency single frequency conversion option using the integrated transceiver ad9371, the similar architecture using gspsadc to replace the integrated transceiver to improve the instantaneous bandwidth, and the direct frequency conversion architecture which can improve the bandwidth but reduce the image suppression performance. Although the signal chain introduced in this paper can be used directly, it is suggested to design based on it. According to the specific system level application, there will be different requirements. With the advancement of design work, the selection of signal chain will be more and more clear.

Reference circuit

Bosworth, Duncan and Wyatt Taylor ADI, 2016.

Delos, Peter. “Overview of broadband receiver architecture.” ADI, 2017.

Hall, bradand Wyatt Taylor ADI, 2017.

Satellite communication system – 5th Edition. West Sussex: John Wiley & Sons, Inc., 2009.

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