Semiconductor memory has been widely used, in which DRAM and SRAM are two common forms of memory. The characteristic of DRAM is that it needs to refresh regularly to save data. As long as SRAM stores data, it will not lose data without refreshing. DRAM and SRAM have their own advantages and disadvantages. This paper discusses the current technical challenges and development prospects of DRAM and NAND.
Development and challenge of DRAM Technology
DRAM technology is evolved from the early random access memory technology. RAM memory temporarily retains the memory state during the read / write operation, and will erase the memory every time the computer is shut down. Ram initially used complex wire and magnet systems, which were bulky and power consuming. DRAM can only keep the data for a short time. It needs to refresh the stored data regularly. For DRAM, it is more complex than SRAM in terms of production. There are many kinds of DRAM chips, such as fpram, fastpage, SGRAM, wram, edoram, DDR ram, RDRAM, etc. DDR ram is widely used and has good performance. DDR SDRAM is the most used memory in computers and one of the most cost-effective memories. In high-end graphics cards, high-speed DDR ram is usually configured to improve bandwidth.
The complexity of today’s DRAM technology is driven by many of the same development challenges that affect the CPU, including multiple patterns, proximity effects, and storage node leakage. DRAM development needs accurate modeling to predict and optimize this impact and avoid yield problems. Challenges such as bit line mandrel spacing and mask offset may be critical for determining the contact area from BL to the effective area, which may lead to poor yield if not addressed.
It is difficult to identify and correlate the specific process parameters that lead to wafer level failures using wafer experiments alone. It is time-consuming and expensive to manufacture test wafers and measure the final contact area on wafers in the process of process change research, which can be avoided by using advanced process modeling technology.
In order to improve the yield of DRAM, the minimum contact area can be determined by modeling the change of BL isolation layer thickness and BL mask offset at the same time. This process change function, together with the built-in structure search and DRC function, can identify the minimum contact location area on the chip. Scanner 3D is a process modeling platform that can perform these types of research. With semulator3d, we can perform process change studies to investigate potential problems with BL core spacer thickness and mask offset. Figure 1 (a) shows an example of using semulator3d to check the effect of BL isolation layer thickness and mask offset on BL / AA contact area. Figure 1 (b) identifies the on-chip location of the minimum contact area.
Figure 1: (a) the relationship between BL / AA contact area and BL isolation layer thickness and mask offset, (b) the minimum contact area required.
Another technology problem in DRAM process development is that the contact point of storage node is adjacent to the adjacent active area, because excessive proximity will lead to device short circuit. It is difficult to trace the root cause of these potential short circuits, but they can lead to catastrophic reliability and yield problems later in the development cycle. Accurate modeling and identification of the minimum gap between capacitor contacts and AA at different z-positions can help alleviate these future reliability and yield issues before lead out.
Figure 2 illustrates the BL to AA contact areas found during process modeling and highlights the minimum gap locations that need to be addressed by process or design changes. These two examples illustrate the complex interaction between processing steps and the resulting impact on DRAM reliability and yield,
Figure 2: virtual wafer manufacturing process model (semulator3d), showing potential short circuit between storage node contact and AA.
Flash memory was invented in 1984 and can be erased and reprogrammed many times. It is used for storage and data transmission in consumer devices, enterprise systems and industrial applications. Flash memory can retain data for a long time, whether the device equipped with flash memory is powered on or off. Flash memory has been transformed from 2D technology to 3D technology (3D NAND), which improves the storage density.
The etching of single-layer 3D NAND structure is very complex, because the holes with very high aspect ratio must be etched with a group of alternate materials. In addition, the bending and inclination of the hole must be avoided in the etching process. In addition, we need to create “slit” etching to separate the adjacent storage cells. The 3D NAND structure increases the complexity of the “ladder” etching required to form word line (WL) contacts. The complete 3D NAND array (modeled as semulator3d) is shown in Figure 3. It illustrates the structural complexity of the latest 3D NAND memory design – it’s a simple single-layer structure.
Figure 3: single layer 3D NAND memory cell modeled by semulator3d.
In the transition process from 2D to 3D flash memory structure, the process complexity increases sharply because 3D structure needs multi-layer column etching operation. Now, most 3D NAND memory stacks are two-tier in height, which increases the extra concern of top-level to bottom misalignment. The problems and concerns of multilayer 3D NAND column etching are shown in Figure 4.
Figure 4: the semulator3d output illustrates the problem of layer misalignment and the resulting column etch offset.
In this figure, we show an example of layer misalignment and the resulting column etch offset. This type of misalignment may be caused by process variability and must be included in any 3D NAND process development project. As can be seen from this example, layer to layer alignment plays a crucial role in creating powerful multi-layer 3D NAND storage cells. Similar to our DRAM example, DOE statistical difference study can be run in semulator3d, which can model 3D NAND multi-layer alignment errors and take corrective measures without spending time and money on wafer based testing.