Phase-locked loops (PLLs) are one of the most versatile, flexible and valuable circuit configurations in electronic systems and are therefore used in many applications. It is used for clock retiming and recovery, as a frequency synthesizer and as a tunable oscillator, just to name a few. As a result, PLLs can be found in many items of RF equipment including radio receivers and test equipment. Depending on its implementation, it can serve frequencies from near DC to GHz and beyond, playing many key roles in systems and circuits.

A PLL is a closed-loop (negative feedback) architecture, and a basic PLL consists of the following blocks (Figure 1):

Figure 1: A basic PLL is a closed-loop negative feedback system where the error between the reference signal and the VCO output is used to correct the output; the low-pass filter is a key element in establishing the loop dynamics.

A Phase/Frequency Detector (PFD) (often simply referred to as a Phase Detector PD) compares an input signal to a reference signal and produces an error signal proportional to its phase difference (remember, phase and frequency are closely related since frequency is the time derivative of the phase); the output of the phase detector typically goes to a charge pump that converts the small current difference into a larger voltage

a low-pass filter (LPF) that shapes the frequency spectrum of the error signal; the design of this filter is usually a mixture of engineering science and intuitive art, and is a major factor in setting many of the dynamics of PLL operation

Voltage Controlled Oscillator (VCO) whose output phase/frequency is controlled by an error signal

An optional divider at the VCO output that causes the PLL to generate a frequency that is a multiple of N of the reference frequency; N can be an integer, and many PLL designs support fractional-N non-integer division

The output of the VCO (and divider, if used) goes to the phase/frequency detector to complete the feedback loop. In operation, the error signal increases as the phase difference increases. This drives the VCO phase in the opposite direction, reducing the error signal. As a result, the phase of the output is locked to the phase of the other input.

When the PLL output closely tracks the input and the error signal is small and relatively stable, the PLL is said to be “phase-locked” or simply “phase-locked”. Depending on the application, the output of the PLL system used in the system is either the output of the VCO or the control signal of the VCO.

Of course, PLLs were originally designed around the 1920s using vacuum tubes. Their popularity expanded significantly with the introduction of the first mass-market PLL in the 1970s as the IC Signetics NE565 for 0.001 Hz to 500 kHz operation. While this section is now clearly outdated (SigneTICs is long gone), its datasheet is archived and available online1.

PLLs can be built using analog, digital, or mixed-signal circuits. Early PLLs were all analog, with an analog phase detector, low-pass filter, VCO, and optional divider; the divider was quickly upgraded to a digital divider to allow integer and fractional integer division. Digital PLLs now replace phase detectors with up-down counters that perform a similar function in the digital domain, and can also use digital filters, with the error signal driving a direct digital synthesizer acting as a VCO.

Due to the modularity of its internal structure, widespread use and widespread application, the PLL is the engineering counterpart of the works of Shakespeare or James Joyce, as it has been the subject of countless articles, papers and books. They provide an extensive analysis of PLLs with extensive qualitative discussions and highly detailed quantitative models; almost all such analyzes begin with the classic work of Gardner and Viterbi2,3.

Available technical papers cover the performance of the PLL, including various noise, jitter, drift, nonlinearity, distortion, and other circuit imperfections in each functional block, as well as the performance of various input signals. These include papers examining PLL operation in the time and frequency domains; some focus on simple first-order models, while others use highly complex models to capture the many real-world nuances of PLL circuits and signals.

PLL parameters meet application goals

As with most electronic circuits, there are some basic parameters that apply to nearly all applications, and some that are more critical in specific situations. By adjusting a few design details of the phase detector, low-pass filter, VCO, and frequency divider, a PLL design can trade off performance between these parameters to best meet application priorities. Top factors include:

Operating Frequency: Nominal, free-running frequency of the PLL and its VCO

Operating Range: The frequency span over which the PLL and VCO will operate. This includes the pull-in range over which the PLL can acquire the signal and achieve lock, and the wider range over which it can maintain lock once achieved

Transition or capture time: The time it takes for the PLL to capture and lock on to a signal that is operating on an external limit, largely determined by the low-pass filter; narrower bandwidth filters have longer capture times, but limit noise and jitter, while wider bandwidth filters have faster response but allow more noise to pass through the PLL system

Noise and Jitter: Any noise or jitter added by the components of a PLL and thus appearing at its output, even for a perfect signal. Overall Noise Figure of Merit (FOM) Expressed in dBc/Hz, there are several different types of FOM

Deadband: When the two inputs to a phase/frequency detector are very close together, the detector may not see this and therefore not produce a false output; this is somewhat analogous to electronic hysteresis or mechanical stiction

Many other factors may also apply to PLLs in different applications, such as spurious-free dynamic range (SFDR), distortion, intercept, and temperature coefficient; a complete list could be long.

PLL ICs continue to improve in terms of frequency, performance, and integration

To achieve the best combination of performance factors for a given application, a PLL user will purchase and connect separate blocks: phase/frequency detector, custom filter, VCO, and other components. Of course, module and hybrid device manufacturers soon offered complete PLLs as fully characterized units by combining multiple individual IC chips and discrete components.

However, the need for higher frequency wireless systems, such as those for software-defined radios, smartphones, radar systems, and many other applications, has been motivating IC suppliers to develop processes and designs that yield high-performance monolithic PLLs. Many of these integrate most or all functional blocks (depending on frequency and required performance), reducing design time, risk, board space and power consumption.

For example, the HMC830LP6GE PLL from HitTIte (now part of Analog Devices) is a fractional-N PLL that operates from 25 MHz to 3 GHz. It targets cellular/4G infrastructure, repeater and femtocells, and communications test equipment, and features ultra-low in-band phase noise of -110 dBc/Hz, FOM of -227 dBc/Hz, and rms jitter below 180 fsec other applications.

The IC includes an integrated VCO (Figure 2), which has traditionally been the most difficult function to integrate while still achieving high overall performance at high frequencies. As with most PLLs, the data sheet has more than a dozen detailed graphs showing many aspects of the PLL’s performance under various conditions. Figure 3 shows the integrated rms jitter of the PLL over the operating range at different temperatures.

Figure 2: Analog Devices’ HMC830LP6GE represents the trend of the past few years: put the VCO in the IC along with the rest of the PLL, extending frequency range without compromising figure of merit.

Figure 3: PLL datasheets often have many performance graphs, such as this one for the HMC830LP6GE showing rms jitter (fsec) versus frequency at -40⁰C, 27⁰C, and 85⁰C; note the stability of performance over this range.

Another PLL with an integrated VCO is Linear Technology’s LTC6948, a 370 MHz to 6.39 GHz fractional-N device that also features ultralow noise. It also includes a reference divider, phase/frequency detector, charge pump, fractional feedback divider and VCO output divider. The normalized in-band phase noise floor FOM is -226 dBc/Hz and the wideband output phase noise floor is -157 dBc/Hz (Figure 4).

Figure 4: Linear Technology’s LTC6948 datasheet includes, among other parameters, a normalized in-band phase noise floor, FOM, and a wideband output phase noise floor; the latter drops from –100 dBc/Hz to –157 at the highest frequency dBc/Hz.

It supports reference input frequencies up to 425 MHz for fast frequency switching. The IC is ideal for applications such as wireless base stations (LTE, WiMAX, W-CDMA, PCS); microwave data links and military/security radios, where it can be used as the heart of a high-speed, tunable 6.39 GHz wideband receiver (Figure 5).

Figure 5: Even highly integrated ICs require passive component support, as shown in this schematic for a high-speed, tunable 6.39 GHz wideband receiver based on the LTC6948.

Maxim Integrated’s MAX2870 is a 23.5 MHz to 6 GHz PLL with fractional/integer-N synthesizer and VCO (Figure 6). The device achieves its ultrawide frequency through multiple VCOs covering 3 GHz to 6 GHz, which can be selected automatically or under user control (via the serial interface); the user provides the loop filter and reference. The phase/frequency detector operates to 105 MHz in integer-N mode and to 50 MHz in fractional-N mode, and accepts reference frequencies up to 200 MHz. The PLL shows excellent 6.0 GHz phase noise performance across multiple divider settings (Figure 7). Applications include wireless infrastructure, test and measurement, satellite communications, and wireless LAN.

Figure 6: Maxim Integrated’s MAX2870 achieves a 6-GHz rating by using multiple internal VCOs that can be selected automatically or actively by the user.

Figure 7: PLL vendors again provide detailed performance specifications, such as phase-noise plots of the MAX2870 over the operating bandwidth, with different division factors.

Although the Texas Instruments LMX2492 fractional PLL (Figure 8) does not include an integrated VCO, it can operate from 500 MHz to 14 GHz using an external VCO; its FOM is -227 dBc/Hz. When combined with a suitable loop divider, it can be used as the heart of a 77 GHz automotive radar system (Figure 9); it also includes ramp/chirp generation for this focused application.

Figure 8: The Texas Instruments LMX2492 PLL does not include a VCO, but achieves 14 GHz performance at an FOM of -227 dBc/Hz.

Figure 9: Targeting applications such as 77 GHz automotive radar, the LMX2492 has the integrated ramp and chirp functions required by radar.

Due to its 200 MHz phase detector response, the PLL can also be used in non-radar applications such as mobile radios, compact radios, radar modules, microwave backhaul, oscilloscopes, spectrum analyzers, land mobile radios, and software defined radios. Despite its high frequency rating, the IC operates from a 3.15 to 3.45 V supply and dissipates only 60 mA.

In addition to RF performance, many PLLs now include SPI or I 2 C serial interfaces, so the system processor can set and change some PLL parameters such as gain, filter bandwidth, or range. This enables the software to adjust these factors in a given circuit to meet changing scenarios, or to allow the same components to be used in multiple designs.


For decades, PLLs have been a key part of many electronic systems used in communications, synthesis, clocking, signal generation, and signal recovery applications. New ICs are pushing performance specifications to new levels in terms of frequency, noise and jitter performance, while integrating more functionality into a single device. The versatility and flexibility of the PLL is further enhanced by adding digital functions within the loop design itself, or as a control function to establish the PLL operating point.


Signetics NE565 Data Sheet

Gardner, Floyd M. (2005), Phaselock Techniques (3rd Edition), Wiley-Interscience, ISBN 978-0-471-43063-6

Viterbi, Andrew J., Principles of Coherent Communication, McGraw-Hill.

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