Clock is the most important signal in FPGA design. Most devices in FPGA system act on the rising or falling edge of the clock. Whether in input, output or between registers, as long as the sampling to the rising or falling edge of the clock is designed, the setup time and hold time will be mentioned.

The setup time (TSU: set up time) refers to the time required for the data to be unstable to stable before the arrival of the clock edge. If the setup time does not meet the requirements, the data will not be stably input into the trigger at the rising edge of the clock;Holding time (th: hold time) refers to the holding time after the data is stable. If the holding time does not meet the requirements, the data can not be stably entered into the trigger.

The two indexes of setup time and hold time show that the device itself is not ideal (sometimes delayed, etc.), and it is this unsatisfactory characteristic that limits the clock working frequency of FPGA.

First of all, we all know that setup time and hold time are determined by the device, which does not mean that they can be changed with the change of your FPGA design. How to calculate the FPGA clock frequency? Without considering the clock delay jitter and other conditions, the delay of a signal from the d end to the Q end of the trigger is assumed to be TCD. After coming out of the Q end, it will pass through the combined circuit delay. Note that even if there is no combined circuit, there is a delay only through the wire. This delay is called tdelay. After this delay, The signal will go to the next trigger and must meet the setup time tsetup of the trigger, otherwise the clock cannot sample stable data.

Detailed explanation of FPGA establishment time and holding time

Therefore, the sum of these three times should be smaller than the clock cycle, otherwise the data cannot enter the next trigger, and it will enter metastable state. Tcd+Tdelay+Tsetup

As for the relationship between FPGA clock frequency and holdup time, TCD + tdelay + tsetup needs to be met during specific designThordup, that is, thordup determines the lower limit of the shortest path, that is, combinatorial logic cannot be too large or too small. This is where hold time works. In fact, it can generally meet the holding time. Generally, it is necessary to meet the establishment time as long as it is considered.

The simple schematic diagram of setup time and hold time is shown in Figure 1, in which we see CLK_ There is a dotted line in the front and back of R3, and the previous dotted line (the leftmost dotted line, the left represents the early occurrence time, and the signal appears from left to right during simulation with Modelsim) to CLK_ The rising edge of R3 is the establishment time, CLK_ The period from the rising edge of R3 to the next dotted line (the rightmost dotted line) is the holding time.

Detailed explanation of FPGA establishment time and holding time

As mentioned in the previous definition of setup time and hold time, there can be no data change during this period, and the data must remain stable. In this waveform, we do not see any change in the data of reg3in during the establishment time and holding time, so we can stably lock the data of reg3in into the output reg3out of reg3.

Some of the same signals, but we found reg3in in CLK_ The establishment time of R3 has changed, and the consequence is CLK_ If the reg3in data latched by the rising edge of R3 is uncertain, the subsequent reg3out value will also be in an uncertain state. For example, in the first clock cycle, reg3in should have a stable low level, but the delay time (TCD + tdelay) on the whole path is too long, resulting in reg3in in CLK_ The data has not stabilized during the establishment time of R3. During the establishment time, the signal level changes from high to low, that is, an unstable state. The result is that the final output of reg3out is not a determined state, which is likely to be a metastable state of high and low, rather than the expected low level.

Let’s take another look at the holding time violation. This time, the data is transmitted too fast (TCD + tdelay > thordup, that is, the TCD + tdelay delay is too small). It should have reached CLK in the next clock cycle_ The data of R3 is in CLK_ The holding time of the previous clock cycle of R3 has not passed. Therefore, its ultimate harm is that the reg3out of the back-end output is in an uncertain state.


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