As DSP chips become more and more powerful, faster, cost-effective, and development tools become more and more perfect, they are widely used in communications, radar, sonar, remote sensing, biomedicine, robotics, control, precision machinery, voice and image processing. As one of the computer interfaces, the USB (Universal Serial Bus) port has the characteristics of potential plugging, fast speed (including low, medium and high modes) and large peripheral capacity (theoretically, 127 devices can be connected), making it a The increasingly extensive interface standard is used in the expansion of peripheral equipment of PC. This paper designs and implements a USB port data acquisition and analysis system based on DSP. The DSP of the system is responsible for data acquisition and operation processing. The processing results are sent to the computer for display and analysis through the USB port. Its structure is shown in Figure 1.

In the structure diagram, CPLD and FPGA realize module interface, including serial-to-parallel conversion, conversion between 8-bit and 32-bit data bus, SRAM and other functions. The sampling results are sent to the DSP for arithmetic processing (FFT transformation, correlation analysis, power spectrum analysis, etc.) through the CPLD, and then sent to the host computer for storage and display by the FPGA and USB interfaces. Computer applications are easy to implement rich graphical interfaces and have a good human-machine interface.

1 Modulo module

This system is mainly used for vibration signal and noise analysis, requiring high sampling accuracy and sampling frequency not exceeding 100kHz. Choose CS5396 of CRYSTAL Company according to the requirement. The chip was originally used for stereo sampling, based on sigma-delta structure, high sampling accuracy, 24-bit resolution, 120dB dynamic range; sampling frequency 32kHz, 44.1kHz, 48kHz, 96kHz optional; internal integrated sample-and-hold, analog low-pass Filter, digital filter, and also have the function of time sampling; two channels are sampled at the same time, serial output, serial data is converted into 24-bit parallel data by CPLD; since the chip range is 4V, differential input, so the analog part only needs Coupled with a simple range amplifier circuit can be. In this way, the analog circuit is very simple, with strong anti-interference ability and high precision.

2 DSP processors

When choosing a DSP processor, the main consideration is its operation speed, bus width and cost performance. The sampling structure of this system is 24-bit, and 32-bit DSP is the best choice; the system needs to carry out real-time signal analysis, modal analysis, etc., and requires higher operation speed, so TI's 32-bit floating-point DSP-TMS320VC33 is selected. The chip adopts Harvard structure, 6-stage pipeline operation, instruction execution cycle 7ns, and peripherals include a DMA controller and a buffer serial port.

The N-point complex FFT transform does about 2N×Log2N real multiplications and 3N×Log2N real-time additions. The multiplication and addition of TMS320VC33 are all single-cycle instructions, taking N=1024, excluding memory access and other time, the time required for one FFT is: 10×5120×17ns, about 0.9ms. And according to the sampling frequency of 96KSPS, the sampling time of 1024 points is about 10ms, which shows that the DSP speed is enough to meet the requirements.

The DSP boot mode is optional. After power-on, the BOOTLOADER residing in the low address space is executed; then the boot mode is judged according to the status of the four interrupt input signals, which can be booted from RAM, ROM or serial port. This system selects the serial port mode. In this way, the DSP program can be directly downloaded from the PC and sent to the DSP interface, so that it can be debugged in the system and has great flexibility.

3 USB ports

The realization of the USB protocol is based on the idea of ​​the network. It is a shared bus, and data is sent in the form of packets on the bus. There are 4 modes of USB data transfer: Bulk Transfers, Interrupt Transfers, Isochronous Transfers, and Control Transfers. When a large batch of accurate data needs to be transmitted quickly, the block transmission mode is generally used; when the real-time data is transmitted, the interrupt transmission mode is used.

When a USB device is plugged into a computer, an enumeration process occurs between the computer and the USB device. The computer detects that a device is inserted and automatically sends out a query request; the USB device responds to this request and sends the Verdor ID and Product ID of the device; the computer loads the corresponding device driver according to these two IDs to complete the enumeration process.

Because the USB protocol is very complex, it is impossible for developers to develop on the underlying basis. Currently, there are interface chips on the market that encapsulate the USB protocol, such as: USBN9602 of NaTIonal Semiconductor, PDIUSBD12 of Plilips, and so on. This system selects AN2131QC of EZ-USB series with MCU core from CYPRESS company. This chip complies with USB1.0 specification (12Mbps), and integrates 8051 MCU core, intelligent USB interface engine, USB transceiver module, memory, serial port, etc. , thereby reducing the chip interface timing. Its internal structure is shown in Figure 2 (the chip part is in the dotted line).

The 8051 code (Firmware) of EZ-USB can be solidified in ROM; a better solution is to download it from the host to the internal RAM through the USB port, so that it is easy to modify, debug and update. The reason why the code can be downloaded is that the enumeration process is automatically completed on the hardware as soon as the chip is powered on, and no Firmware is required. After the enumeration is completed, it can be used as a USB device (called the default USB device) to communicate with the computer, and firmware download can be performed at this time. After downloading, the 8051 kernel leaves the RESET state and starts executing code. USB devices can be reconfigured through Firmware, a process called re-enumeration.

In EZ-USB, the default USB device interface includes 14 Endpoints, as shown in Table 1.

Table 1 Default USB endpoint (Endpoint)

The data communication between the computer and the USB device mainly includes two aspects: one is to read the sampling data; the other is to send control commands to the USB device. Sending a control command first sends a command packet (message), and then sends subsequent data or reads response data from the device as appropriate. Therefore, according to the function of the EZ-USB chip, the 6 Endpoints in the default configuration are directly used.

Endpoit OUT2 BULK: used to send control command packets.

Endpoint IN2 BULK: Receive DSP messages from USB devices.

Endpoint IN4 BULK: used to read data from USB devices, such as reading sampling data, configuration parameters, etc.

Endpoint OUT4 BULK: used to send data to USB devices, such as downloading 8051 programs, downloading FPGA programs, etc.

Endpoint OUT6 BULK: It is used for auxiliary judgment. When the PC finishes transferring a large amount of data to the USB device, it writes any data to this port to notify the USB device.

Endpoint IN1 INT: used to read the response signal from the USB device, such as the sign of whether the download of the FPGA program is successful, etc.

On the basis of the default configuration, you can write suitable codes. If you are experienced in 8051 programming, you can write Firmware without debugging tools.

The Firmware structure of this system is based on the continuous service of the message queue, that is, a message queue is constructed, and when a message from any party (DSP or computer) is received, it is put into the message queue. The reception of the message is achieved through the interrupt service routine. When a message is processed, the next message is taken from the message queue for processing. This software structure is very simple, the thinking is clear, and it is very beneficial to debugging.

USB device drivers are based on WDM. WDM-type drivers are kernel programs, which are different from standard Win32 user-mode programs. A layered approach is used. Through it, the user does not need to directly communicate with the hardware (especially obvious in the USB driver), and only needs to access the hardware through the interface number provided by the underlying driver. Therefore, the USB device driver does not need to program the hardware specifically, and all USB commands, read and write operations are transferred to the USB device through the bus driver. However, the USB device driver must define the communication interface with the external device and the data format of the communication, and must also define the interface with the application program.

The driver program of this system is developed using the object-oriented language C++ on the basis of C++ompuware Numega Driver-Works. Driver-Works can quickly construct the framework of the driver. Two classes are mainly constructed: Class USBDAC and class USBDACDevice. Class USBDAC inherits class Kdriver and is responsible for some operations to be done when loading drivers and creating functional device objects. Class USBDACDevice inherits class KpnpDevice and is the main part of the driver, responsible for device start, stop and data communication with the device. API function calls and implementations of CreateFile(), ReadFile(), WriteFile(), DeviceIO-Control(), CloseFile(), etc. are also done in class USBDACDevice.

The definition of Class USBDAC is as follows:

class USBDAC : public Kdriver




/*Driver Entry (),

virtual NTSTATUS DriverEntry(PUNICODE_STRING RegistryPath);

/*AddDevice(), create a Device object. Call its constructor to initialize the device, create the name of the device, etc. */


Int m_Unit;


The definition of Class USBDACDevice is as follows:

Class USBDACDevice : public KpnpDevice


// Constructors




~USBDACDevice ();

// Member FuncTIons


//Add your own member function


NTSTATUS USBDAC_StartADConversion(void);

NTSTATUS USBDAC_StopADConversion(void);


NTSTATUS USBDAC_Download8051(KIrp);




The FPGA module mainly realizes the data buffering between the single-chip microcomputer and the DSP, the conversion between the 8-bit data line and the 32-bit data line, and the switching between the single-chip synchronous serial port and the DSP buffer serial port. The FPGA is required to realize abundant internal RAM and accurate clock control. Choose XCV50TQ144 of XILINX Company according to need. The device uses an SRAM look-up table structure with features such as in-system reprogrammability (ISP) and run-time reconfiguration. When the system is initialized, the FPGA program is downloaded from the USB port, and the line configuration is performed through the serial port of the single-chip microcomputer.

This system can be widely used in vibration and noise testing and analysis. Various dynamic testing and signal processing applications can be developed under WINDOWS95/98/NT, and various DSP algorithms that have been programmed can be loaded as required to enable signal analysis, modal analysis, acoustic analysis, environmental testing, and long-term recording. and other functions.

Responsible editor: gt

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