1. System structure of undersampling receiver

Cellular base station (BTS: base station transceiver) is usually composed of several different hardware modules, one of which is the transceiver (TRX) module that performs RF receive (Rx) and transmit (TX) functions. In the old analog amps and tacsbts, a transceiver can only process one full duplex RX and TXRF carrier, so it needs many transceivers to provide enough carrier. Today, worldwide, analog technology has been replaced by CDMA and WCDMA, and GSM was adopted in Europe 10 years ago. In CDMA, multiple calling users can use the same RF frequency. In this way, a transceiver must process the signals of multiple calling users at the same time. At present, there are a variety of CDMA and GSM design schemes, and BTS manufacturers have been committed to exploring ways to reduce cost and power consumption. Optimizing single carrier solutions or developing multi carrier receivers are effective solutions. Fig. 1 is a structural block diagram of an undersampling receiver commonly used in BTS equipment.

In Figure 1, Maxim’s 2ghzmax9993 and 900mhzmax9982 mixers can provide the required gain and linearity for many designs, and have extremely low coupling noise, so there is no need for passive mixers with high loss. Max2027 and max2055 work in the first and second medium frequency stages of the receiver respectively. These two devices are in the whole gain adjustment range? OIP3 can reach + 40dbm. The data converter in Figure 1 uses max1418 (15 bit, 65msps) and max1211 (12 bit, 65msps). In fact, Maxim’s other data converter devices with sampling rate can also meet most design requirements. If the second down converter in Figure 1 is omitted (shown in the dotted line), the circuit shown in Figure 1 becomes a single down converter structure.

Design of under sampling receiver system based on high performance ADC and RF device

2. High performance device recommendations

2.1 low noise ADC device max1418

The structure of the undersampling receiver shown in Fig. 1 has strict requirements for the noise and distortion of the ADC. In the receiver, the useful signal with low level is digitized alone or accompanied by useless and large amplitude signals that need more attention. Therefore, in order to make the receiver work normally, the effective noise coefficient of ADC should be calculated according to the extreme conditions of these two signals (i.e. the smallest useful signal and the largest useless signal). For smaller analog input signals, the dominant thermal noise and quantization noise in the noise base of ADC determine the noise figure (NF) of ADC.

Max1418 series products are especially suitable for baseband applications when finput < fclock / 2. When the converter works in this frequency band, these devices with excellent baseband characteristics will have the best dynamic range, including max1419 for 65msps clock rate and max1427 for 80msps clock rate. Their baseband SFDR (spurious free dynamic range) can reach 94.5dbc.

In fact, max1418 can also work with 14 bit interface devices. At this time, SNR will be slightly lost, while SFDR will not be affected.

When the front-end gain of ADC is 36dB, the single tone blocking level exceeding – 30dBm at the antenna end will exceed the input range of ADC. According to the CDMA2000 cellular base station standard, the maximum blocking level allowed at the antenna end is – 30dBm. At this time, the front-end gain needs to be reduced by 6dB. In this way, within the margin allowed by the standard specification? The maximum blocking signal allowed to be added to the ADC may be larger. Assuming a margin of 2dB is left and the front-end gain is reduced by 6dB, the maximum blocking level at the antenna end will become – 26dbm and the maximum allowable input signal of ADC will become + 4dbm. In other words, when single tone blocking occurs, the total interference (noise + distortion) allowed by the cellular standard will deteriorate by 3dB relative to the reference sensitivity, and how to allocate 3dB between noise and distortion is a problem that designers should consider.

2.2 max1211 converter with primary down conversion structure

If enough SNR and SFDR indexes can be obtained in the higher if section, the under sampling circuit can be used in the primary down conversion structure. Max1211, 12 bit, 65msps converter of Maxim company is designed with this structure. Its pin is compatible with the upcoming 80msps and 95msps converters. This series of devices can directly sample the input if signal with frequency up to 400MHz. In addition, it also has its advanced performance, For example, the clock input can be differential signal or single ended signal, and the clock duty cycle can be adjusted between 20% and 80%. In addition, max1211 is also designed with a data valid indicator (to simplify the clock and data timing), and adopts a small 40 pin QFN (6x6x0.8mm) package, binary complement and gray code digital output format.

Compared with the double frequency conversion structure, the primary converter has obvious advantages. Since the second stage down conversion mixer, the second stage if gain circuit and the second stage Lo synthesizer are omitted, the number of components and circuit board space can be reduced by about 10%, and the cost will be greatly reduced.

2.3if amplifiers max2027 and max2055

Maxim also provides numerical control gain and high-performance IF amplifier with 1dB increment per stage. Among them, max2027 NC gain amplifier? DVGA? Using single ended input / single ended output mode, it can work in the frequency range of 50MHz to 400MHz, and the noise coefficient at its maximum gain is only 5dB. Max2055 is a single ended input / differential output DVGA, which can drive high-performance ADC in the frequency range of 30MHz to 300MHz. A step-up transformer can be used to provide differential drive between the differential output of max2055 and the differential input of ADC, which is conducive to the balance between output signals. These two DVGA usually work at 5V bias and can reach OIP3 of + 40dbm in the whole gain setting range.

2.4 high linearity mixers max9993 and max9982

In the receiving circuit, the mixer often bears a large input signal with strict performance requirements. Ideally, the amplitude and phase of the output signal are directly proportional to the amplitude and phase of the input signal, and this proportion is independent of the LO signal. Therefore, the amplitude response of the mixer is linear with the RF input and independent of the lo input signal.

However, the nonlinearity of the mixer will also produce some unwanted mixing signals, called spurious response. These spurious signals are the response generated by the clutter signal reaching the RF port of the mixer in the IF band. The useless stray signal will interfere with the operation of the useful RF signal. The IF frequency of the mixer can be given by the following formula:

fIF = ±mfRF ± nfLO

Here, if, FRF and Flo are the signal frequencies of their respective ports respectively, and m and N are the harmonic order after mixing the FRF and Flo signals.

Maxim’s integrated (or active) balanced mixers max9993 and max9982 have attracted much attention because of their better performance than passive mixing schemes. When m or n is even? The balanced mixer can suppress a certain spurious response. An ideal double balanced mixer can suppress all responses with an even number of M or n (or both). In the double balanced mixer, if, RF and lo ports are isolated from each other. A properly designed unbalanced transformer can make the mixer overlap in if, RF and lo bands. The features of max9993 and max9982 include: low noise figure, including LO buffer, low Lo drive, Lo switch allowing two Lo inputs, excellent Lo noise characteristics, etc. In addition, there are RF unbalanced transformers at RF and lo ports.

Because these mixers of Maxim are embedded with lo buffers with excellent Lo noise performance, the requirements for lo power supply are reduced. Generally, the mixing of Lo noise and high-level input blocking signal will reduce the reception sensitivity, while max9993 and max9982 can reduce the impact on the reception sensitivity in case of blocking due to the inclusion of low-noise LO buffer. For example, suppose that the sideband noise of VCO input signal is – 145dbc / Hz, while the typical value of Lo noise characteristic of max9993 is – 164dbc / Hz. In this way, the composite sideband noise will only decrease from 0.05dbc/hz to – 144.95dbc/hz. Using this method, users only need to provide a low-level LO signal for the mixer to ensure that the mixing characteristics of the receiver will not be reduced due to the performance of the max9993 built-in LO buffer.

In addition, there is a tricky second-order spurious response, also known as half intermediate frequency (1 / 2If) spurious response. For low-end injection, the mixer order is: M = 2, n = – 2; For high-end injection, the mixer order is: M = – 2, n = 2. During low-end injection, the input frequency causing the half if parasitic response is lower than the desired RF frequency. Fig. 2 shows the useful FRF? fLO? The specific location of FIF and useless fhalf if frequency. In fact, the desired RF frequency is the mixing of 1909mhz and 1740mhz LO frequency, and the resulting if frequency is 169MHz. Although the RF and if carrier bandwidth of CDMA is 1.24mhz, it is represented here as a single frequency signal with the frequency as the central carrier frequency. In this example, the intermediate frequency of 1824.5mhz causes spurious signal. because:

2fHalf-IF - 2fLO =fIF

Therefore: 2 × 1824.5MHz-2 × 1740MHz=169MHz

In general, the total amount of inhibition (also known as 2 × 2) the spurious response can be predicted according to the second cut-off point IIP2 of the mixer. Figure 3 shows the 2 of max1993 × 2imr or spurious value. The signal level in the figure is the mixer input level calculated by input IP2 (IIP2) performance. The specific calculation formula is as follows:


=2 × 70dBc+?- 75dBm?= 70dBc+?- 5dBm?


Since the typical stray response 2rf-2lo provided by Maxim’s max9982900mhz active filter is 65dbc, the calculation method of IIP2 is as follows:


=2 × 65dBc+?- 70dBm?= 65dBc+?- 5dBm?


3. Concluding remarks

When the receiver gain requirement is not high, the 15 bit ADC chip max1418 of Maxim has excellent noise performance, so it can withstand large blocking level or interference level with the smallest AGC. Max1211adc series products are suitable for primary frequency conversion receiving structure, and its first if input frequency can reach 400MHz. In addition, max9993 and max9982 mixers can provide the required linearity, and have the characteristics of low noise figure and high power gain. Therefore, passive filters can be omitted in the process of receiver design. The typical value of OIP3 of max2027 and max2055dvga in the whole gain adjustable range is about + 40dbm. The receiver composed of these elements can improve the performance of low-cost solutions to a higher level.

Responsible editor: GT

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