With the development and wide application of computer technology, especially in the field of industrial control, the application of computer communication is particularly important. Although serial communication greatly reduces the connection between devices, it brings problems such as serial/parallel conversion and bit counting, which makes serial communication technology more complicated than parallel communication technology. Serial/parallel conversion can be implemented in software or in hardware. Using software to realize serial transmission mostly uses circular shift instructions to transmit a byte from high to low (or low to high) one by one. Although this method is simple, it is slow and takes up a lot of CPU time. system performance. A more convenient method is to use hardware. Currently, the commonly used LSI chips for the serial interface of microprocessors are UART (Universal Asynchronous Receiver/Transmitter), USART (Universal Synchronous Asynchronous Receiver/Transmitter) and ACIA (Asynchronous Communication Interface Adapter). No matter what kind of chip, one of their basic functions is to realize serial/parallel conversion. It is these serial interface chips that compensate for the complexity of serial communication. This paper applies EDA (Electronic Design Automation) technology to design and implement UART based on FPGA (Field Programmable Gate Array)/CPLD (Complex Programmable Logic Device).

1. Overall design

The whole design includes two parts: the design of UART based on FPGA and the program design of the host computer based on VB6.0. The design of UART adopts the modular design idea, which can be divided into three modules: FPGA data transmission module, FPGA baud rate generator control module and data reception module. The host computer program adopts Mscomm control of VB 6.0, which can be divided into two parts: screen design and function design. The serial port adopts the standard RS-232 protocol, and the main parameters are selected as: baud rate 9 600 bit/s, 8 effective bits, no parity bit, and 1 stop bit.

2. UART structure and frame format

UART mainly includes receiver and transmitter. The asynchronous signal received from the asynchronous receiving input signal SIN completes the serial/parallel conversion through the receiver to form an asynchronous data frame; the transmitter performs parallel/serial conversion on the 8-bit data sent by the CPU and sends it out from SOUT. Functions include microprocessor interface, TBR (transmit buffer), TSR (transmit shift register), frame generation, parallel-to-serial, RBR (receive buffer), RSR (receive shift register), frame generation, serial-to-parallel . The structure of UART is shown in Figure 1.

The frame format of UART includes line idle state (idle, high level), start bit (start bit, low level), 5 to 8 data bits (da-ta bits), parity bit (parity bit, optional option) and stop bit (stop bit, the number of bits can be 1, 1.5, 2 bits). This format uses start and stop bits to synchronize characters. There are generally configuration registers inside the UART, which can configure the number of data bits (5 bits to 8 bits), whether there is a check bit and the type of check, and the number of stop bits (1, 1.5, 2 bits) and other settings.

3. Design and implementation of UART

UART is a widely used serial data transfer protocol. The UART allows full-duplex communication over the serial link. The serial peripheral uses the RS-232-C asynchronous serial interface, which is generally realized by the application-specific integrated circuit (UART). Chips such as 8250, 8251, NS16450, etc. are all common UART devices. Such chips are quite complex, and some contain many auxiliary modules (such as FIFO). Sometimes it is not necessary to use the complete UART function and these auxiliary functions, or use If the FPGA/CPLD is used, then the required UART function can be integrated into the FPGA. The core functions of the UART are integrated using VHDL, making the entire design more compact, stable and reliable.

The three modules of UART (transmitter, receiver and baud rate generator) are designed respectively below, and the simulation results are given.

3.1 Transmitter Design

The block diagram of the UART serial transmitter module is shown in Figure 2. DIN is 8 bits of data and the rest are 1 bit.

As can be seen from the block diagram of Figure 2, the serial transmitter contains an 8-bit THR (transmit holding register) and TSR (transmit shift register). During reset, pin TRE is high. After data is loaded into TSR, pin TRE goes low. After the transmission is completed, TRE becomes a high level. When it is detected that the input WRN goes low, the serial data transmission process is automatically enabled. The 1-bit start bit (logic level 0) is transmitted first, and the data in the THR is automatically loaded into the TSR in parallel. Then, the fixed-length data bits are shifted out of the TSR, followed by the parity bits. Finally, a stop bit (logic level 1) is generated, marking the end of a frame. Serial data frames will be transmitted at 1/16 of the internal clock frequency. If the content in THR is not empty, after a serial data frame is transmitted, the next data frame is sent immediately. This automatic process enables data frames to be sent back-to-back, increasing the bandwidth of data transmission. When no data is sent, the SDO pin remains high.

The transmitter outputs 1 bit every 16 clock cycles, followed by 1 start bit, 8 data bits (assuming 8 data bits), 1 parity bit (optional), and 1 stop bit. Introduce the length of the sent character and the sending order counter no_bits_sent, and some of the implemented VHDL programs are as follows:

The transmitter function simulation results are shown in Figure 3. The parallel input DIN hexadecimal number is 56, the WRN input changes from 1 to 0, the shoulder sends the program, the counter starts to count, the serial output SDO is 0010101101, and after the transmission, TRE becomes a high level. The start bit is 0, 8 data bits, and 1 stop bit, which proves the correctness of the sending module.

3.2 Receiver Design

The block diagram of the UART serial receiver module is shown in Figure 4. DOUT is 8 bits of data and the rest are 1 bit. The receiver contains an 8-bit RBR and RSR. The state of the RBR can be indicated by the pin DATA_READY meter. When the data in the RBR is valid, DATA_READY becomes a high level, indicating to the CPU that the same data can be taken.

This design only requires simple transceiver functions, so no error detection program is designed. After the program detects the start bit, it counts 16 clock cycles, starts to receive data, shifts the input RSR, and finally outputs the data DOUT. Also output a data reception flag signal to mark the completion of data reception. Part of the implemented VHDL program is as follows:

The simulation results of the receiver function are omitted. The serial input RXD is 0010101101, and each bit occupies 16 clock cycles. Once it is detected that the input RXD is 0, the counter starts to count and starts to receive data. After receiving, the flag bit becomes high. The simulation results prove the correctness of the receiving module.

3.3 Design of Baud Rate Generator

The receiving and transmitting of the UART are performed according to the same baud rate. The clock frequency generated by the baud rate generator is not the baud rate clock frequency, but 16 times the baud rate clock frequency, and the purpose is to accurately sample at the time of reception to bring out asynchronous serial data. Calculate the baud rate divider according to the given crystal clock and the required baud rate. Part of the implemented VHDL program is as follows:

The baud rate function simulation results are omitted. The input frequency is 20 MHz, the waveform period is 50 ns, and 20 MHz/(9 600 bit/s×16 bit) = 130. From the simulation results, it can be seen that the half cycle of the output waveform is 65 times the input clock cycle, which proves that the wave Correctness of the bit rate generator module.

4. Host computer programming

This text uses VB 6.0 to carry on the design of the host computer program, realize the serial communication between PC and FPGA. The following is the design process of a host computer sending and receiving test communication program, through which serial communication with FPGA can be performed. The default value of the baud rate is “9600, N, 8, 1”, which means that the communication port used is transmitted at a speed of 9 600 bit/s, without character verification, each time the data is 8 bits, and stops bit is 1 bit. The baud rate (unit is bit/s) can be 110, 300, 600, 1200, 2400, 9 600, 14 400, 19 200, 28 800. The check digit is: E even check, N no check, O odd check, S blank. The correct data bit values ​​are: 4, 5, 6, 7, 8 (default). The correct stop bit values ​​are: 1 (default), 1.5, 2.

After compiling and emulating the UART program, download it to the EPlK30TC144-3 chip of the FPGA. Introduce a crystal frequency of 20 MHz; connect a switch to the sending enable terminal and reset terminal; respectively connect a diode to the status output flag TRE and DATA-READTY to indicate the status; set the baud rate to “9 800, N, 8, 1” . The format of the serial data frame is: start bit 0, 8 data bits, no parity bit, 1 stop bit. Connect the serial sending and receiving ports of the UART to the serial receiving and sending ports of the computer’s RS-232 respectively, so as to communicate with the PC serially; the parallel input DIN is connected to the parallel output DOUT; test program.

5. Conclusion

In the realization of serial communication between FPGA and PC, the program is downloaded to the chip to verify the correctness of the design. At present, there is no better tool that can analyze the working conditions and data of the FPGA in real time after downloading. Through serial communication, you can send control commands to the FPGA to make it perform the corresponding operations, and at the same time send the required data to the PC through the serial port for corresponding data processing and analysis, so as to judge whether the FPGA works according to the design requirements. This text focuses on UART and discusses the realization method of serial communication between FP-GA and upper computer. The high-level language VB is used to realize the communication between the host computer and FPGA.

Responsible editor: gt

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