Time to digital conversion (TDC) technology was originally a subject in experimental nuclear physics. With the continuous development of science and technology, high-resolution TDC technology has been applied in high-energy physics, radar, laser and sonar ranging, communication direction finding, remote sensing imaging and so on. The all digital integrated circuit has the advantages of simple process, low cost and low design difficulty Therefore, all digital TDC has also become the concern of researchers. A fully digital analog-to-digital converter (ADC) is reported in the literature. This method is essentially based on the all digital TDC, with a power of 0.8 μ M A full digital 18 Bit ADC is realized in 0.45mm2 CMOS technology. The chip can achieve 12 μ V resolution at 10 ms / s sampling rate, and the nonlinearity is ± 0.1%. The principle of TDC and ASIC of the system are reported in the literature. A 13 bit TDC is realized in 1.5 μ m CMOS process with an area of 1.1mm2. Its resolution is only about 0.5ns of delay time of a single gate.
In this paper, the methods in the literature are transplanted to PLD, which includes FPGA and CPLD. It can effectively shorten the R & D cycle, improve the design flexibility and reusability, reduce the design cost and tape risk. Once the design is successful, the soft core can be decoupled from the process, making the design reuse very convenient.
The TDC designed in the literature uses ring delay gate unit (RGDS) to realize time division. The structure is shown in Fig. 1. The design uses the ring delay unit composed of delay gate as the measurement basis of time signal, decoder decoding as low-level digital output, followed by ring counter recording cycle times as high-level digital output. Finally, the two groups of digital are combined as the measurement result output, which effectively reduces the number of delay gates used and reduces the chip area.
To transplant this method to FPGA / CPLD design, we need to solve the following problems: 1. The design and synthesis of delay gate; 2. The discrete delay time of single gate circuit makes each gate have relatively equal delay time; 3. Consider the highest working frequency of counter; 4. Optimize the designed circuit to make it occupy less chip resources under the condition of meeting the target The target chip is economical and applicable.
In this paper, the design of the above structure is implemented on Altera’s max series chip. The simulation results show that the max 7000 chip in the max series can achieve the highest time resolution of 3.5 ns, and the hardware test is also successful.
2. Working principle of TDC system based on RGDS
The all digital TDC system based on RGDS is composed of four parts: ring delay unit, latch and XOR unit, coding unit, count and latch unit. Figure 2 is the circuit schematic diagram of the first three parts in Figure 1. RGDS consists of 63 non gates and an and gate. The state of the circuit node Po to p63 can reflect the position of the PA pulse in the non gate chain. The detection of the position is realized by the latching and XOR unit. In general, the output and input of the non gate are in inverse phase, but for the non gate which PA signal just reaches in the non gate chain, the output of the non gate is opposite The XOR gate is responsible for detecting the non gate with the same output and input in the non gate chain. The position of the signal arriving can be obtained, and then the transmission time of the signal on RGDS can be calculated.
The counter and latch unit is a 7-bit counter, which counts every time PA signal is transmitted to terminal p63. The double edge counter is used, which is equivalent to the “Coarse Count” in the whole TDC process. A complete count of TDC process can be formed by coarse counting and “fine counting” of lock memory and XOR unit between P0 and p63. The value of the fine count is formed in the coding unit as the low order output of the total count. Because 64 non gates can form 6-bit output, plus the high-7 bits of coarse counting part, the final output of the TDC system is 13 bits. Therefore, the resolution of TDC system is determined by the delay of single gate in RGDS, while the dynamic range of time measurement is mainly determined by the bit width of counter. The ASIC with RGDS structure realizes 1.5 μ M The chip area is 1.1mm2 and the resolution is 0.5ns.
3. PLD implementation of TDC
To transplant this method to FPGA / CPLD design needs to solve some problems. EDA tools expand the logic function of any circuit, not the specific circuit structure, so it is difficult to obtain the required series delay gate structure. Because the internal layout of programmable devices can not guarantee the consistency of delay gates, the conversion accuracy of TDC will be affected, and even can not work normally in serious cases, The counting frequency of the general counter is limited by many factors. Too high working speed may lead to code skipping, which also limits the structure design of RGDS.
3.1 design of ring delay unit
As mentioned above, it is not feasible to directly transplant the ring delay unit in the above-mentioned ASIC design to FPGA / CPLD. Even if the method of schematic input is adopted, the required functional structure can not be obtained after synthesis by the synthesizer. The reason is very simple. When EDA tool is used for synthesis, the synthesis results are given based on the logic relationship between the circuit input and output, and the odd number of non gates are combined into a single The purpose of this design is to obtain the delay information between all levels of not gates, so simply transplanting cascaded not gates in ASIC design can not achieve this goal. The solution is to change the non gate to two port input device, such as using two input and gate or NAND gate instead The connection mode of one input port is similar to that of non gate, forming a series connection relationship, connecting all redundant input ports of all gates to high level. This port can also play a control role in simulation. However, if the number of gates is too small, a situation may occur, that is, the total delay on all serial gates is less than the minimum required for normal operation of the counter At this time, the counter will produce the phenomenon of missing or skipping code, which will cause disorder of RGDS system. If the number of serial gates is too large, the possibility of gate delay time discretization will increase. At the same time, the working speed of encoder also determines that the number of gates should not be too small. Therefore, a compromise design should be achieved through simulation.
3.2 delay discreteness of delay gate
Different from ASIC, it is difficult for designers to predict the situation after EDA software layout and routing, and the results of PLD layout and routing with different structures and performances are not the same. Therefore, it is difficult to predict the delay time of a single gate. Even if a data is obtained through the simulator, the situation will be the same in the hardware experiment, and the delay time of a single gate is the basic guarantee of the accuracy of the whole system Therefore, it is necessary to study the applicable methods.
This paper considers from three aspects: 1. By reducing the number of gate circuits in delay loop circuit, the possibility of discrete gate delay time can be effectively reduced, and coarse-grained chips can be selected as far as possible, resulting in large basic logic function blocks and the possibility of series gates being configured in the same macro cell; 3. Continuous interconnection chips should be selected as far as possible, because the wiring delay is relatively fixed and predictable It can effectively reduce the error caused by wiring. As mentioned above, the number of serial gates should be balanced between the working speed of the counter and the encoder. According to Xilinx’s index, the minimum time of a 16 bit counter is 4.3ns, that is, it can reach the counting frequency of 232.558mhz. Under the condition of lower operating frequency, it is generally reliable to determine the number of delay gates.
Through the simulation of two cycles of RGDS system for most chips of max series, except for max5000 and max9000, which have not been tested, the single gate delay time of various chips is 3.4-5.1ns. The RGDS adopts a delay unit composed of 8 gates, and realizes a TDC system with a resolution of 3.5ns on MAX7000 chip. The counting unit works stably at 34.72mhz and the counting time is 28.8ns.
3.3 design circuit optimization
This is an indispensable part of this design. For example, when MAX + PLUSII software is used, the encoder in RGDS unit before optimization has a high bit error rate and can not work normally. After optimization, stable and accurate data can be output. It can be seen that design optimization plays an important role in transplanting this method. Taking MAX + PLUSII as an example, the general process of optimization is still illustrated. The settings of software optimization switch are as follows: 1 Because max series chips are selected in this design, the multi-level synthesis for max5000 / 7000 / 9000 device is selected; 2. In the area and speed optimization options, the area optimization is selected to make RGDS be allocated to the same lab as much as possible; 3. Turn on “slow slow slow rate” to reduce switching noise, and turn on “XOR” To reduce the chip area. 4. Turn on the “turbo bit” and “parallel expanders” switches to optimize the coding by software.
4. Circuit realization, simulation and test results
Based on Altera’s MAX + PLUS II 9.23, this design is implemented on MAX series chips. Figure 3 shows the timing simulation results of MAX7000 series, where P0 to P7 are the circuit nodes behind the single gate of RGDS circuit, CT1 [7 0] is the control end of each delay gate circuit in RGDS, that is, the interconnection of redundant input terminals in all two port gates. When RGDS works normally, RGDS is set to high level; rst is the system reset signal, Q1 is the counter output, which is the high 13 bit output of TDC system, is the coarse counting part, and Q0 is the encoding output of RGDS, which is the low 3-bit output of the TDC system, which is the fine counting part Considering the relationship between the delay of the counter and the output delay of the RGDS code, we should try our best to make it synchronous to avoid the code dislocation.
In order to solve the hardware test of the designed TDC, a signal control circuit is specially designed. The TDC of the circuit can measure the pulse width of the continuous pulse generated by the signal generator, and the resolution can be estimated from the measurement of the pulse width. Limited to the condition, the hardware measurement adopts the target chip max7000s series EPM7128SLC84-15, and the voltage is 5V. Figure 4 shows the relationship between the input pulse width and the measured count value, with a total of 85 values measured. The abscissa is the signal period (NS) of sp1641b function signal generator, its corresponding frequency range is 1.4-3.2mhz, and the ordinate is the count value. The linear relationship between the two can be seen from the curve in the figure. Using the simulation results of EPM7128SLC84-15, the resolution of 9.8ns and TDC can be obtained. After measurement, the measurement system can distinguish the pulse width difference of 4.14-4.49ns in 85 test data, which indicates that the actual resolution of hardware is higher than the simulation result. Fig. 5 is the enlarged picture of signal period from 160 to 210 ns in Fig. 4. It can be seen that the count value has no code hopping and only a small fluctuation, indicating that the design is completely reasonable and feasible. Because 7000s is a slow circuit, according to the measurement results, if MAX7000 series chips are used, the resolution of 3.5ns can be achieved or higher than the simulation results.
The simulation and hardware test show that the design system can count accurately, all functions meet the expected requirements, and the correctness and integrity of the whole design are verified. After optimization, the comprehensive report of max series epm7064lc44-7 chip shows that its 1250 gates use 54%, and the highest conversion rate is 3.5ns, which shows the design idea and implementation of this paper The method is feasible.
In order to reduce the possibility of realizing the 16 bit delay gate in the system, the 16 bit delay gate structure is used to ensure the stability of the system. A TDC system with the highest resolution of 3.5ns is implemented on MAX series chip MAX7000. Simulation data and hardware test show that the counting result is stable and accurate. Because the design is implemented by VHDL language, this design can be easily transplanted to other PLD based designs.
Editor in charge: GT