(source: micro computer information center, Li Sen; Zhang Chunxi; Li Baoguo; Lin Heng, special thanks here!)

1 Introduction

Strapdown inertial navigation system using fiber optic gyroscope is a kind of navigation system with great development potential. For the core component of fiber optic gyroscope, especially high-precision fiber optic gyroscope, the drift caused by ambient temperature can not be ignored, so it is necessary to control the temperature of the system. Temperature control circuit is the hardware basis of the whole temperature control system, which involves temperature acquisition, communication with microprocessor, serial output, control of digital to analog conversion chip and other components. This paper presents an efficient and practical FPGA interface design, which can coordinate the orderly work of various components, realize data transmission accurately and quickly, and strictly control the signal timing.

Overall structure of temperature control circuit

Design of temperature control circuit interface based on PLD

The overall structure block diagram of the temperature control circuit is shown in Figure 1. It includes seven channel temperature sensor, DSP, 232 interface chip, DAC, back-end control circuit, host computer and FPGA. FPGA interface is the core of the whole circuit. Among them, the temperature sensor uses Dallas company’s DS18B20, which uses 1-wire bus protocol and only needs one data line for communication. DSP adopts tmsvc33 of TI company, which can realize high-speed floating-point operation. MAX3232 of Maxim company is used as the interface chip, which supports the transmission rate up to 120kbps. The DAC adopts tlv5620i of TI company, which is an 8-bit 4-channel digital to analog conversion chip controlled by 4 serial signals. FPGA uses ep1k100 of ACEX series of Altera company. It has high clock frequency, rich internal resources, and provides a large number of programmable IO pins, so it is very convenient to configure. The interface of temperature control circuit based on FPGA plays a very important role in the whole circuit. The high-speed parallel structure of FPGA provides a reliable guarantee for the performance of the whole circuit. The work flow of temperature control circuit is shown in Figure 2. FPGA communicates with seven channel temperature sensor, reads temperature value, stores it in internal memory, and updates it once per second. FPGA sends interrupt signal to inform DSP to read the temperature value stored in FPGA. DSP calculates the control quantity according to the current temperature value and control algorithm. Then the temperature value and control quantity are packaged into a frame and sent

Give it to FPGA. FPGA stores the data sent by DSP in the internal memory, and then operates the data to generate the output signal. On the one hand, FPGA sends data to 232 interface chip, and then sends data to PC through 232 serial port. The upper computer can observe the change of temperature value and control quantity in real time through monitoring software, which is convenient for system debugging and evaluation; on the other hand, the control quantity is extracted from the data and output to DAC serially, and the digital control signal is converted by Da and then output analog control voltage to back-end control circuit to realize the closed-loop control of seven channel temperature.

4. Communication interface between FPGA and peripheral circuit the communication interface between FPGA and peripheral circuit mainly includes four parts: communication interface with temperature sensor, DSP, 232 interface chip and DAC.

(1) Communication interface with temperature sensor

DS18B20 is used as the temperature sensor in this scheme. It communicates through the very simple 1-wire bus. Because of the simple hardware, the communication protocol is complex. To realize the communication interface with it will occupy a lot of FPGA on-chip resources, and this scheme needs seven channels of temperature acquisition, so it is particularly important to optimize the program design, reduce redundancy and save resources [2].

(2) Communication interface with DSP

The combination of DSP and FPGA has become a very popular mode in today’s digital circuit. FPGA is very suitable to cooperate with DSP. In this scheme, the communication interface between DSP and FPGA is mainly composed of data bus, address bus and some control signals. FPGA and DSP are connected by 8-bit data bus, and data are transmitted in byte form in parallel. DSP addresses FPGA’s on-chip resources through address bus. The control signal mainly includes reset signal, interrupt signal and read-write signal.

(3) The communication interface between FPGA and 232 interface chip is realized by sending and receiving two data lines. In this scheme, there is only one-way data transmission from the temperature control system to the upper computer, so only one sending data line is needed to complete the communication with the 232 interface chip.

(4) Communication interface with DAC

In this scheme, tlv5620i chip of TI company is selected as DAC. It is an 8-bit 4-way voltage digital to analog converter. Its digital control is based on the serial bus composed of four signal lines. Including CLK, data, load and LDAC. Logic design of FPGA

After the overall scheme, hardware structure, workflow and interface protocol of the temperature control circuit are determined, the logic design of FPGA can be carried out. The logic design of FPGA is the most important part of the whole temperature control circuit interface design. It is based on Verilog hardware description language. Good FPGA logic design should be clear timing, stable operation, clear results and save resources. It can ensure the reliability, stability and efficiency of the whole system. The logic module diagram of FPGA is shown in Figure 3. FPGA internal logic is divided into reset module, DS18B20 interface module, bus control module, DSP interface module, dual port RAM module, 232 interface module and DAC interface module.

(1) The reset module generates a global reset signal. Is the highest priority of all modules. After the system is powered on, the module will pull the reset signal down for 1 second, and then pull it up to reset other modules in DSP and FPGA.

(2) DS18B20 interface module is used to communicate with DS18B20, read and store temperature value. It contains two sub modules.

1、 Temperature acquisition module

The module implements the communication protocol with DS18B20. First, the DS18B20 is initialized by an initialization sequence, including a reset pulse sent by the host and a presence pulse sent by the slave. After the pulse is detected, it means that the initialization is completed, and the module will send the ROM operation command. In this scheme, skip ROM matching is performed. The memory operation command is then sent. Temperature conversion and temperature reading are completed in this part. Each reading and writing operation should be carried out in strict accordance with the reading and writing time slot of DS18B20. The module has high complexity and takes up a lot of resources, so it is an important module in the whole FPGA. There are seven channels of temperature acquisition modules in this scheme, and their parallel structure makes it convenient for the system to realize the real-time monitoring of seven channels of temperature. 2、 Temperature memory module

The main component of the module is a 14 * 8-bit memory, which is used to store seven channels of temperature values. Each channel needs two 8-bit registers. After storage, wait for DSP to read.

(3) DSP interface module this module is mainly used to communicate with DSP. It contains three sub modules. 1、 DSP write signal synchronization module DSP data writing is completed under the control of write signal. Because DSP and FPGA use different clock sources, the write signal generated by DSP cannot be synchronized with the master clock of FPGA. This will result in write data errors. The module is used to synchronize DSP write signal with FPGA master clock. 2、 In this scheme, the temperature value is updated once every second. After the temperature value is updated, DSP is informed to read the temperature value by interrupt signal. The module is used to generate an interrupt pulse with a period of 1 second.

3、 The addressing module is used to address the resources in FPGA chip, and the addressing is controlled by the address bus of DSP. Read and write the required data accurately.

(4) The data bus between DSP and FPGA is bidirectional, and the bus control module is used to control the data flow of the bus. When DSP reads the temperature value from FPGA, the bus control module connects the temperature storage module with the data bus and outputs the data. When DSP writes data to FPGA, bus control module connects data bus with dual port RAM module and inputs data.

(5) Dual port RAM module this module mainly realizes the following three functions: when the DSP writes data, it stores the data in the internal memory; when the data is stored, it sends the control quantity to the DAC control module; it communicates with the serial port sending module to output all the data in sequence.

(6) 232 interface module this module is used to realize serial port data output, it includes two sub modules: first, the serial port baud rate module, the serial communication protocol requires that both sides of the data transceiver have the same baud rate. The module is used to set the baud rate of serial communication. 2、 Serial port sending module

After the dual port RAM module stores the data, it will send a flag signal to the serial port module. After receiving this signal, the serial port sending module outputs the data stored in the dual port RAM module serially.

(7) DAC interface module, which includes two sub modules: first, DAC clock module, DAC needs a specific frequency range of clock to drive. The module is used to generate the clock signal to drive the DAC. 2、 DAC control module

The module is used to generate DAC control signals. Its basic principle is to store the 7-channel control output of dual port RAM module in internal memory, and then generate control signals such as CLK, data, load and LDAC according to DAC interface protocol, which will drive DAC to work and convert digital control values into analog voltage values.

Concluding remarks

FPGA interface design needs to consider many factors, such as hardware connection, workflow, interface protocol and logic module. This paper introduces the temperature control circuit interface design of fog inertial navigation system based on FPGA from the above aspects, which has been applied in the actual system. After verification, the interface meets the requirements of the system and works well. The design of FPGA interface described in this paper is reliable, stable and efficient. It can provide useful reference for other related applications. The author’s innovations are as follows: seven channel parallel temperature acquisition structure; multi-function temperature control circuit interface structure; temperature value and control quantity packaging and unpacking data transmission protocol; efficient and stable multi interface FPGA logic design; multi-function temperature control circuit interface structure;

Editor in charge: GT

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