For embedded system developers, it is of great significance to deeply understand the addressing principle of the storage system and effectively manage the storage system for the correct and efficient design of embedded system hardware and underlying software programming. At present, the most commonly used memories in embedded system include EEPROM, flash, normal DRAM and flash Sync.DRAM And so on. The memory used in this paper includes SDRAM and flash. S3C4510B (hereinafter referred to as 4510) microprocessor is built on the arm core ARM7TDMI. The address bus of ARM7TDMI is 32 bits, the internal system bus of 4510 is 26bit: SA [25:0], and its external address bus is 22bit: addr [21:0]. How to decode between them? Why can we access up to 16MB of memory address space with only 14 external address buses This paper tries to answer these questions. Finally, the design of the storage system based on S3C4510B at the hardware level, i.e. the interface design and the implementation of the storage system programming in uClinux are introduced.
2. The principle of storage system based on S3C4510B
2.1.the relationship between 32-bit address bus and 26 bit internal system bus
ARM7TDMI regards memory as a linear set of many bytes growing up from zero, 0 to 3 bytes as the first word, 4 to 7 bytes as the second word, and so on. Its address bus is 32-bit, while the 4510 internal system bus is 26 bit, that is to say, the maximum addressable space is 226 bytes, that is, 64MB address space of 0x0000000-0x3fffff. Obviously, the internal address bus of RISC microcontroller 4510 built on ARM7TDMI only uses the lower 26 bits of ARM7TDMI’s 32-bit address bus, and is connected one by one.
2.2.4510 addressing principle
4510 adopts the unified addressing method, which maps the on-chip and off chip memories, special function registers and external I / O devices of the system to 64MB address space. At the same time, for the convenience of management, the address space is divided into several memory groups (banks), including 6 ROM banks, 4 DRAM banks, internal SRAM and special register groups, and each memory group corresponds to one The size and position of each memory group can be set by configuring the base pointer and end pointer. The above figure is the control register of DRAM (0 ~ 3). [19:10] is the DRAM group base pointer, and the set value is shifted 16 bits to the left, which is the starting physical address of DRAM group. Therefore, we can deduce that the location of each memory group is set and distinguished by the high 10 bits SA [25:16] in the 26 bit system address bus of 4510. [29:20] is the end pointer of the DRAM group. The set value is shifted 16 bits to the left, which is the end physical address of the DRAM group. Therefore, we can also deduce that as long as the base pointer and tail pointer in any group of control registers are set, the location and size of this group of memories in the 64MB addressable space of 4510 can be determined. On the other hand, we can draw the following conclusion: for any system address to be addressed, we can judge which memory group it belongs to by the high 10 bits of the address And the lower 16 bits of the address are its offset address in the determined memory group. In fact, 4510 is addressed through this mechanism. 4510 subtracts the top 10 bits of the request address from the base pointer of all memory groups to achieve group selection and calculate the offset address. When the group is selected and the offset address is calculated, 4510 will generate the corresponding group selection signal and use the offset address to address the external memory through the physical address bus, thus completing the whole process of addressing.
2.3.26 bit internal system address bus and 22 external address buses
4510 can support 8, 16 and 32-bit interfaces with external memory by setting the value of extdbwihd register. The address decoding from SA [25:0] to addr [21:0] depends on the data width of different interfaces. When 4510 sends a word access signal, the storage system ignores the lower 2 bits SA [1:0], that is, SA  is connected with addr , and so on, until SA  is connected with addr . Similarly, when a half word access signal is sent, the storage system ignores the lower bits SA , that is, SA  is connected with addr , and so on, and so on. The purpose of doing this is to determine the total address of 4510 in schematic design The line can be conveniently connected with the address bus of the memory one by one.
2.4 addressing problem of SDRAM
Take the SDRAM chip hy57v1620hg as an example. The internal memory organization of the chip is 4banks * 1m * 16bit, that is, there are four banks, each bank has 1m half words (16bit). Because there are row address latch pin Ras and column address latch pin CAS in the chip pins, we can regard each bank as a storage unit array table as shown in the figure below. Each table represents a 16bit data storage unit. In practical work, first of all, the bank address and the corresponding row address are issued at the same time, and then the column address addressing command and the specific operation command (read or write) are sent at the same time. At this time, we select the bank, row address and column address successively, so we only determine a storage unit in the storage unit array table. So far, we can understand the problem of using only its 12 address lines to access 8MB address space.
3. Specific design of storage system interface circuit
From the analysis in Section 2.2, we can know that the so-called chip select signal is the memory group select signal for 4510. 4510 uses NRCS “5:0” as the chip selection signal of flash and nsdcs [3:0] as the chip selection signal of SDRAM. From reference 3, we can see that the ldqm and udqm pins of hy57v1620 play the role of data input / output mask. How does the storage system use these two pins? When 4510 executes half word data read instruction ldrh, byte data read instruction ldrb and other instructions in memory, these two pins play a role. For example, when ldrb is executed, 4510 will send a control signal to make udqm of sdram1, ldqm and udqm of sdram2 effective, that is, they mask the upper 24 bits of 32-bit data for byte reading. Ldqm is the abbreviation of low (byte) DQ mask. Udqm is the abbreviation of upper (byte) DQ mask. DQ refers to the input / output data of SDRAM.
The above figure is the schematic diagram of the storage system circuit. The parallel design of two hy57v1620 is to give full play to the performance of 32-bit MPU
4. Implementation and configuration of storage system in embedded operating system uClinux
The so-called implementation and configuration of storage system in uClinux is essentially to set the control registers of each memory group of 4510. Here we use uclinux-samsung-20020318 tar.gz edition. The macro for configuring all 4510 related special registers of the storage system is defined in linux-2.4. X / include / ASM armnommu / arch sampling / hardware. H. Some of the codes are as follows:
#Define dsr0 (2 0 / * ROM bank0) data width is half word*/
#Define dsd0 (3 < 12) / * ram bank0 data width is words*/
#define ROM_ BASE0_ R ((0x00000000) 16) the base pointer of 10 / * ROM bank0 is 0x000*/
#define SDRAM_ BASE0_ R（（0x01000000》》16）《《10）？ /*The base pointer of ram bank0 is 0x0100*/
The real code for storage system mapping is Linux-
2.4. The partial codes of X / arch / armommu / boot / compressed / head. S are as follows:
#ifdef CONFIG_ ARCH_ SAMSUNG
LDR R0, = syscfg / * sets the value of the system register*/
adr r0，SDRAM_ SYSINIT_ Reset / * set initialization storage mapping*/
ldr r0，=SYS_ INIT_ Base / * this macro definition is located in the hardware. H mentioned above and is the address of the first register in the external storage register group*/
This paper describes the problems about the storage system that I encountered in the process of embedded system design. I hope that developers confused by the same problems can get inspiration and help from this paper, so that they can understand and design the hardware and software of the whole system from a deeper level.
Editor in charge: GT