According to the design requirements, it is the most difficult point to realize the maximum voltage gain ≥ 60dB in a wide signal bandwidth (0-10mhz), and the gain can be adjusted continuously or preset with 5dB step. The other difficulty is that the maximum output voltage of the post stage power amplifier module under 100Q load is more than 10V. Because the low end of bandwidth is 0 Hz, that is, DC signal, the zero drift of amplifier circuit is also a difficult problem to solve. In addition, the cost should be considered in the design of the whole amplifier.
1. Data processing and control core selection
Scheme 1: AT89S52 + FPGA is used to realize signal gain control, data processing and man-machine interface control. Because the system does not involve a lot of data storage and complex processing, FPGA resources can not be fully utilized, and the cost is high.
Scheme two: the unified control and data processing of the whole system are realized by using single chip microcomputer. Msp430f449 is a 16 bit ultra-low power consumption microprocessor, which has rich peripherals and strong computing ability. It supports on-line programming and is very convenient to use and has high cost performance. Therefore, scheme 2 is adopted.
2. Signal gain control and power amplification scheme design
Scheme 1: a multi-stage amplifier circuit composed of triode is used to achieve a gain of more than 60 dB, and a post stage power amplifier is built by using discrete components. The cost of this scheme is low, but it is difficult to match transistors, the circuit design is complex, the step adjustment of gain is difficult to realize, the work point debugging is tedious, and the circuit stability is poor, and it is easy to generate self excitation phenomenon.
Scheme 2: using integrated chip, such as using low noise, precision controlled variable gain amplifier AD603 as gain control core device, using high voltage output broadband operational amplifier to complete power output.
Ad3603 has high temperature stability, and its gain (DB) is linear with control voltage (V). Accurate numerical control can be realized by using D / a output control voltage. But the cost is high. The circuit has high integration, simple design and short design cycle.
To sum up, scheme 2 is adopted.
2、 Overall scheme design and system block diagram
The overall block diagram of the system is shown in the figure below.
Overall scheme Description: the system input signal through the front stage amplifier circuit, the later stage program-controlled amplifier and the last stage power amplifier, achieving the maximum voltage gain of 90dB. The back stage power amplifier uses high voltage output broadband operational amplifier to improve the output voltage RMS. Msp430f449 is used as the core of data processing and control. The control voltage of AD603 is adjusted by D / a converter, and the gain is adjusted by program control. The amplifier gain is × 1, × 10, × 100 by switching the back stage programmable amplifier circuit channel through relay Control function of.
The passband selection is realized by switching two elliptic filters by relay. The control voltage of AD603 is changed continuously by manually adjusting the continuously adjustable potentiometer to realize the function of continuous gain adjustment.
Zero drift problem. The zero drift and offset of the amplifier are mainly produced by the input of AD603. When the gain of AD603 is adjusted, the output DC offset voltage is also different. Before each test, the input of AD603 is short circuited, and the output voltage of the zeroing amplifier is sampled by the internal ADC of msp430f449. The corresponding regulating voltage is controlled by the single chip microcomputer and digital algorithm to control the output of the zero adjusting amplifier. In this way, the DC zero drift is suppressed and the function of automatic zero adjustment is realized.