1 Introduction

The INS/GPS integrated navigation system has been widely used in the military field and the civil field of motion carrier. The INS is the core part of the integrated navigation system, which involves the collection and processing of many sensor data such as multiple gyroscopes, multiple accelerometers and temperature sensors, and has high real-time requirements for system operations. For the research of navigation computer system, many scholars have done a lot of useful work. Most of the existing solutions for sensor data acquisition use a multi-channel AD chip with a delta-sigma structure to collect 6-channel inertial device signals, which results in that the data acquisition of the 6-channel signals cannot be carried out at the same time, which leads to a decline in the navigation accuracy of the integrated navigation system under high dynamics. . This text uses AD converter AD1274 produced by TI Company and FPGA EPlS30 main selection chip produced by Altera Company, and expounds the realization method of the integrated navigation system.

2 Data collection

The sensors of the integrated navigation system include 3 low-cost micromachined gyroscopes (AD'ADXRS150), 3 micromachined accelerometers (AD'ADXL210), pressure sensors (Motorola'MPX4115A), two-axis magnetic compass (Honeywel'HMC1022), A temperature sensor (TI'TMP275) and GPS. These sensors need to be sampled at the same time to meet the requirements of the integrated navigation system. The system uses the high-precision analog-to-digital converter ADS1274 produced by TI. ADS1274 is a high-performance 24-bit delta-sigma AD converter with 4-channel synchronous sampling input channels, and the output has two modes of serial and parallel, as shown in 1.

A total of 3 pieces of AD1274 are used in this system, one piece is used for data acquisition of 3 gyroscope signals; the other piece is used for data collection of 3 accelerometers; the third piece is used for data collection of 2 magnetic azimuth sensors and 1 pressure sensor , the output signal of the temperature sensor is a digital signal, and no analog-to-digital conversion is required. Each piece has one AD remaining for redundant systems for further research.

In order to overcome the deviation of navigation calculation caused by the asynchronous data acquisition time of the sensor output signal, in addition to the AD1274 with 4-channel synchronization, the control of the data acquisition system uses an FPGA with a parallel mechanism, and the chip selects Altera's Cyclone low-cost. FPGA EP1C6Q240.

3 Design of the integrated navigation system

Features of the integrated navigation system include:

Data acquisition Collect various sensor signals (gyroscope, accelerometer, magnetic compass, thermometer, barometric elevation, etc.);

Preprocessing adopts digital filtering technology to preprocess the collected sensor signal;

Navigation calculation uses navigation algorithm to perform data fusion processing;

Output navigation information The function information of the system's position, speed and attitude is output to the motion carrier control system for navigation instruction and motion control.

Navigation calculation and navigation information output are realized by TI's OMAP5912. The principle of the integrated navigation system is shown in Figure 2.

OMAP5910 is a dual-core processor produced by TI, which integrates the TMS320C55XTMDSP core and the ARM9TDMI core on a single chip to achieve the best combination of application performance and low power consumption. This unique architecture not only provides the low power consumption, implementation signal processing functions of a DSP, but also provides the command and control functions of an ARM. It fully utilizes the advantages of DSP for addition and multiplication operations, performs real-time operation of navigation parameters, and uses ARM's super transaction management functions to perform navigation data output, display, and control of servo mechanisms.

4 FPGA design

4.1 FPGA logic design

The main work of FPGA is: synchronously generate the working sequence of each ADC; synchronously send command words; synchronously receive, digitally filter and store the converted data of each ADC; provide a logic interface with an external processor. The logic unit inside the FPGA mainly includes: state machine (State), ADC controller, digital filter, RAM block, interface unit, etc. The corresponding structure is shown in Figure 3.

The state machine State is the control unit inside the FPGA. It runs round and round at a fixed rhythm and instructs the ADC controller to complete various operations. According to the different processes of FPGA sending and receiving ADC data, the state machine can be divided into four different state cycles. For the sending process, the four state cycles are: setup cycle, sending cycle, sampling cycle, and conversion cycle; for the receiving process, the four state cycles are: setup cycle, receiving cycle, storage cycle, and idle cycle. Since the sending and receiving processes can overlap in time, the state flow chart is shown in Figure 4, where the value of Count is determined according to the sampling frequency, and can be selected with reference to different systems.

The ADC controller is the main execution unit inside the FPGA, and it performs corresponding work according to the rhythm and status indication of the state machine. RAM is a data storage unit inside the FPGA, which is used to store the data converted by each ADC. The interface unit is a function coordination unit inside the FPGA, which provides a bridge for the external processor OMAP to access the FPGA. When the OMAP writes the ADC initialization configuration word to the FPGA, the interface unit sends the configuration word to the ADC controller and resets the state machine at the same time; When OMAP reads the data of the RAM block inside the FPGA, the interface unit decodes the access address of the external processor, selects the corresponding RAM block, and sends the accessed data to the bus of the external processor.

For low-cost micro-machined gyroscopes and accelerometers, due to the immature technology of micro-inertial instruments, there are still deficiencies in performance and accuracy, such as outliers and large drifts in data output, which seriously affect the normal operation of the system and Therefore, it is necessary to preprocess the data output by the micromechanical sensors (gyroscope, accelerometer, pressure sensor, etc.) before performing the integrated navigation data fusion algorithm. This system adopts the method introduced in the literature to design the FIR filter using FPGA. Considering the overall requirements, digital filter design indicators: passband 0~20 Hz; passband attenuation not greater than -3 dB; transition bandwidth 5 Hz; minimum attenuation in stopband not less than -20 dB; frequency 100 Hz.

FPGA completes the synchronous acquisition of each ADC data through the coordinated work of these internal structural units, as well as the seamless interface with the external processor OMAP.

4.2 Logic Simulation

According to the structure and function of the logic unit inside the FPGA, in the QuartusⅡ development platform provided by Altera, the above logic is designed with VHDL language, and the function is simulated. Its design results have been realized in the company's EP1C6, and the performance is stable.

5 Conclusion

This paper proposes an integrated navigation system based on FPGA and high-precision ADC, which has the characteristics of short development cycle and high degree of integration. Both software and hardware are implemented by programming, the design is flexible, easy to modify, and has received good results in practical applications. Through the sports car test, the navigation position accuracy of the integrated navigation system based on FPGA and high-precision ADC: horizontal position 6 m (without DGPS), 5 min 300 m (without GPS signal); attitude accuracy: roll and pitch angle 0.3°~0.5 ° (with GPS), 0.7°~1.0° (without GPS); heading angle 0.4° (with GPS), 2° (without GPS). Experiments show that the design scheme is feasible and achieves the expected purpose.

Responsible editor: gt

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