With the rapid development of high-speed railway and the modern development trend of locomotive and rolling stock, the requirements of reliability, safety and real-time communication of train bus are further improved. The domestic traditional field bus is difficult to meet the requirements. The multi-functional vehicle bus (MVB) is a fast process control bus, which can provide the best response speed and is suitable for vehicle bus MVB has gradually become the communication bus standard of next generation vehicles. With the increasingly wide application of MVB communication network, the Ministry of Railways of China has taken it as a standard platform for train communication. Domestic railway rail transit equipment manufacturing enterprises have also successively imported train microcomputer control systems equipped with MVB network from abroad. Some departments have also carried out localization research and independent research and development of MVB related products. In order to ensure the compatibility of equipment produced by different equipment manufacturers, and to verify the protocol consistency of MVB products, it is necessary to test the protocol consistency of each MVB equipment, so as to improve the success rate of MVB equipment interconnection. In the process of MVB design and implementation, it is an important work to correctly analyze the running state of MVB bus. Therefore, the analysis of MVB network is a necessary means to further study MVB technology.
Introduction to MVB protocol
MVB can use three kinds of different physical media in the physical layer: non isolated short distance electrical medium ESD, isolated medium distance electrical medium EMD and long distance optical fiber medium ogf. All media use 1.5 MBGs transmission rate. The media access of MVB to the bus adopts the master-slave mode of centralized control and periodic distribution. The only bus manager on the bus, that is, the master device, centrally controls the media access. The main equipment divides the bus band (each basic cycle) into two parts: periodic pre allocation (periodic phase) and non periodic on-demand allocation (occasional phase). The periodic phase is used for the transmission speed, motor current, driver’s command, etc. of the urgent and short periodic process variable data, while the occasional phase is used for the transmission of long but infrequent non periodic message data, such as equipment diagnosis or travel information. In order to meet the requirements of two kinds of data communication services provided by MVB on the link layer, TCN standard defines a bus class independent real-time Protocol RTP on MVB. From the perspective of application layer, RTP provides two types of communication services: process variables and message services. The protocol of process variable service only includes physical layer, link layer (divided into MAC sub layer and LLC sub layer) and application layer, which is used to transmit periodic control commands and control variables to achieve the real-time control requirements. The link layer completes most of the work of the protocol mainly through the LPI processing port and communication cache operation of the link process data interface; the application layer handles the access of process variables through the AVI application variable interface.
Analysis and structure design of 3 MVB bus
The process variable data transmitted on MVB network is in the form of master-slave frame response and periodic broadcast. The bus analyzer can be connected in MVB network to monitor the frame data transmitted in MVB network at any time. MVB bus analyzer can be divided into four parts: decoding module, control module, storage module and PC / 104 interface module. The overall block diagram of the system design is shown in Figure 1. The decoding module collects the data on the bus and transmits the data to the control module. The control module writes the data to the memory module according to the different conditions of the frame. The memory module is used to store the frame data and provides PC / 104 interface to the upper computer.
3.1 decoding module
In MVB network, Manchester code is adopted, data transmission rate is 1.5 Mb / s, sampling frequency is 16 times of data transmission frequency, i.e. 24 MHz (period is 41.67 NS), so a perfect data waveform should be 8 low-level and 8 high-level, as shown in Figure 2 (a). In the non ideal state, the duration of high and low level of Manchus code will change randomly in a limited range. When the change is continuous longer or continuous shorter, it may cause the counter out of step, as shown in Figure 2 (b).
The fundamental reason for this out of step is that the counter’s return to zero is not controlled, and the trigger of sampling action is controlled by the counter. The return to zero of 4B counter is the result of accumulation driven by 24 MHz clock (cyclic accumulation of 0000-1111). Therefore, when the level continuously becomes longer or shorter, the counter that should return to zero at the end of each Manchus code cycle can not return to the initial state of “0000” when the next Manchus code cycle comes. The constant accumulation of such errors will lead to out of step decoding (bit out of step). Here is to take the following measures to solve this problem: detect the inevitable level jump edge in each Manchus code, and take this jump edge as the control signal of the counter; when this signal is valid, the counter will be placed in the ideal state, so that in each Manchus code, the counter can synchronize with the MVB serial signal once.
3.2 control module
The control logic receives the signal decoded by the decoder unit. If the frame is incomplete or CRC check error, add error flag 2 to the memory unit directly; if the frame is complete, judge the master-slave frame; if the main frame, add flag 0 to the memory unit directly; if it is a slave frame, judge whether the arrival time of the slave frame meets the requirements; if it meets the requirements, add flag 1 to the memory unit Unit. Otherwise, the flag 2 is added to the memory unit, and the state transition of the whole control logic is shown in Figure 3.
3.3 storage module
Communication memory is an important part of MVB Bus Analyzer, which is responsible for storing the data of MVB bus communication, so MVB and PC will frequently access the communication memory to read data through PC / 104 interface module. There are three ways to realize the communication memory: using the internal RAM resources of FPGA; using the internal registers of FPGA; using external memory, such as SRAM, E2PROM, etc. Finally, the internal RAM resource of FPGA is selected to realize the communication memory. The reasons include the following points: now advanced FPGAs all have on-chip RAM resources of different sizes. If external memory is used, some expansion circuits are needed, which leads to the complexity of the circuit, increases the instability and brings the access delay of external registers. After comparison, it is a better scheme to use FPGA internal RAM to realize communication memory.
3.4 PC104 interface module
PC104 interface has four access modes: 8-bit memory, 16 bit memory, 8-bit I / O and 16 bit I / O. Here is the 8-bit memory mode, logic implementation and wiring are relatively simple. Through PC104 bus interface, the device can be connected to PC104 bus and used as a standard device on PC104 bus. PC can access the device and communication memory through PC104 bus. A kind of device is only one of the devices controlled by CPU, so the allocated memory space is limited. The memory space is from 0xd0000 to 0xe0000. Address decoding is needed to map the communication memory of the device to the memory area of the CPU. PC104 adopts stack structure, single row double row pin and Jack, P1: 64 pin, P2: 40 pin, 104 bus signals in total. The definition of interface pin is shown in Table 1.
4 experiment and Application
The MVB network built in the laboratory is shown in Figure 4. The MVB network is composed of MVB main device, bus manager D412 of duagon company, MVB class I device 1 designed by mvbc01 chip and MVB class I device 2 and device 3 designed by FPGA.
The MVB Bus Analyzer is connected to the MVB network. The host computer reads the memory module of the MVB bus analyzer through the PC / 104 bus. The MVB Bus Analyzer completely stores the data on the bus. Among all the data obtained, the incomplete slave frame data is shown in Table 2.
According to the analysis of the collected incomplete frame data, the main reasons for the incomplete frame are that the frame header is not correct (the high level or low level time is too long or too short), CRC check error (the generated CRC is not correct), the frame data is not complete, and the ending time is too short. According to the corresponding relationship of master-slave frame data, when the main frame is transmitted on the bus, the device should send but not send the slave frame. In view of these problems, we can check the logic design errors in FPGA and other programmable devices one by one, and reduce the occurrence of incomplete frames through improvement, so as to ensure the reliable transmission of data of self-developed MVB devices in MVB network.
Based on the study of MVB, a MVB analyzer with PC104 bus interface is developed. The MVB bus analyzer has realized the recording of all data transmitted by MVB network, which is conducive to further master the MVB bus network data transmission technology, and is ready to verify the interconnection and interoperability of MVB devices.
Editor in charge: GT