Embedded systems used in real-time control systems often need to measure analog quantities. The usual method is to use MCU to generate acquisition and control sequence control analog-to-digital converters, and to read the converted results by interrupting or querying. The acquisition control sequence generated by the MCU will occupy more system software and hardware resources. In a general complex multi-channel signal measurement and control system, the MCU needs to perform data storage, communication, data processing and other tasks. If it is required to frequently generate the control sequence of the analog-to-digital conversion controller, it will affect the performance of the system. In severe cases, it will become the bottleneck of the system. In this paper, CPLD is used to generate the control sequence of A/D converter, so that CPLD mainly realizes the function of A/D sequence control, and DSP mainly realizes the function of closed-loop control algorithm.
1 The overall structure of the system
The system takes DSP and CPLD as the core, the analog signal is connected from the analog multiplex switch CD4067, and the CPLD is used to enable its input. Use the GPIO port of the DSP as the channel number selection of the analog multiplexer. A/D converter uses MAX194 of MAXIM Company, and its control sequence is produced by CPLD. When the A/D conversion is finished, an EOC signal will be generated, which is used as an external interrupt of the LF2407. When the DSP receives the conversion end signal, it enters the corresponding external interrupt program and uses the SPI bus to receive the digital converted from A/D. value and handle it accordingly. The overall structure of the system is shown in Figure 1.
2 Hardware Design
2.1 Main control DSP chip TMS320LF2407A
The main controller of the system adopts TMS320LF2407A, 3.3 V static CMOS process, 40 MIPS, with 16-bit address bus, 16-bit data bus, 3 independent storage spaces, including available 64 kB program space, 35.5 kB data space and 64 kB of I/O space. When accessing different storage spaces, DSP has corresponding pins as strobe signals, PS corresponds to program space, DS corresponds to data space, and IS corresponds to IO space, all of which are active low. This system maps the MAX194 A/D converter to the I/O space 0000H-7fffH, and its enabled logical expression is: CS=A15+IS. The multi-channel analog switch is mapped to 8000H-ffffH in the I/O space, and its enabling logic expression is: CS=A15+IS. Where IS is the I/O space strobe signal line.
TMS320LF2407A has 32 kB FLASH program memory and 2.5 kB RAM data memory inside. FLASH can meet the needs of DSP system program storage, and the data memory of 2.5 kB may not be enough. Moreover, the program is generally written in RAM in the research and development stage, so the design selects the CY7C1021V33 SRAM of Cypress Semiconductor, the SRAM is 64 kB, and 0000H-7ffffH is set as the program space and 8000H-ffffH as the data space in the design. The logical expression of the extended SRAM is: CS=(A15+PS+DS)(A15+PS+DS). In the formula, CS is the chip select signal line of the SRAM, A15 is the 16th address line of the DSP, PS is the program space strobe signal line, and DS is the data space strobe signal line.
2.2 Analog-to-digital conversion module MAX194
The TMS320LF2407A chip has a built-in 16-channel A/D converter, but it can only input unipolar voltage, with only 10-bit resolution, and the precision is not ideal, so it needs to expand the A/D converter chip. After many comparisons, the author chose the MAXl94 chip of MAXIM Company, which is a kind of analog-to-digital converter of gradual comparison type, which has the characteristics of high precision and low power consumption. There is a calibration circuit inside the MAX194 to ensure linearity over the full temperature range, and no external adjustment circuit is required. Separate analog and digital supplies minimize digitally coupled noise. Its main features are: 14-bit resolution, 1/2 LSB nonlinearity, 82 dB signal-to-noise ratio, low power consumption, unipolar or bipolar input, and tri-state serial output.
The MAX194 has two interface modes: synchronous and asynchronous. Synchronous mode: During the conversion process of MAX194, one data bit is output after each conversion. At this time, SCLK should be grounded, and CLK is used as the conversion clock of the ADC and the shift output clock of the serial interface. Asynchronous mode: The DSP can only read out the conversion result after the MAX194 has completed a conversion, and then start the next conversion. This mode slows the MAX194’s continuous conversion speed.
Use CPLD to control MAX194, can easily control MAX194 to work in synchronous or asynchronous state, without any changes to the hardware circuit, only need to modify the program in the CPLD. This design sets the MAX194 in the asynchronous working mode, and the timing diagram of the MAX194 asynchronous mode is shown in Figure 2.
According to the timing diagram shown in Figure 2, the sampling control process is divided into 4 states:
(1) Initial state: The MAX194 sampling control signal is initialized, and each sampling control state is set to zero.
(2) Start sampling state: Set the start conversion signal START of MAX194 low and keep it for at least two CLK cycles.
(3) Conversion end state: Set the start signal START of MAX194 to high and detect the conversion end state signal EOC. When it changes from high level to low level, it means that the conversion has ended. Therefore, this state is the same as the previous state to see if the EOC signal changes. If there is a change, it will go to the next state. If there is no change, it will continue to cycle in this state until the EOC signal changes.
(4) The output state of the conversion result: the chip enable signal CS of MAX194 is set low, and the DSP transmits the data obtained by A/D conversion to the DSP through the SPI port.
According to the description of the above working state, the program of the A/D conversion sampling control module is written using VHDL language, and the simulation is carried out. The simulation result is shown in Figure 3. It can be seen from the simulation diagram that the designed A/D conversion control module fully meets the design requirements.
3 Software Design
TMS320LF2407A is based on C2000 platform and provides two programming languages: C/C + ten languages or assembly language. Among them, the program written in C language is highly readable and portable, and greatly shortens the development cycle, but the execution efficiency is low, and it is not easy to diagnose when the program is wrong. Assembly language programs are efficient but cumbersome to write. The usual practice is that the core part of the program (that is, the part that is frequently called) is written in assembly language to improve the execution efficiency of the entire system, and the part that does not require high real-time performance is written in C language to reduce the complexity of the program and improve the readability of the program and modifiability. This paper adopts the multi-file structure written in C language and assembly language, mainly including the design of the main program and the interrupt program that reads the A/D conversion result.
The software flow is shown in Figure 4. It is mainly divided into three parts: SPI configuration part, analog switch control part, A/D conversion control and reading of conversion results.
3.1 SPI configuration section
For the LF2407A, the serial SPI peripheral interface has 9 registers to control its operation. In this design, the SPI interface of LF2407A is set in the master mode. In this mode, the master controller is used to send dummy data, and the slave controller sends data. The master controller can initiate a data transfer at any time because it controls the SPICLK signal. But software determines how the master controller detects when the slave controller is ready to send data. The initialization procedure of the SPI interface module is as follows:
3.2 Analog Multiplexer Gating Section
Since the multi-channel analog switch is mapped between 0X8000-0XFFFF in the I/O space of the DSP, in the DSP program, a read operation is performed between 0X8000-0XFFFF, and the channel selected by the GPIO of the DSP is gated. The signal is output to A/D converter MAXl94 by CD4067.
The holding time of the low-level signal CS generated by the read address is determined by the waiting time for accessing the I/O space, and the effective delay time is guaranteed by setting the waiting state register.
3.3 MAX194 conversion control part
Because A/D maps the I/O space of DSP between 0x0000 and 0x7fff, similar to the analog multiplexer, a read operation also needs to be performed on this space.
The multi-channel data acquisition system has strong practical value in the embedded measurement and control system. In this paper, a design based on TMS320LF2407A and EPM570T100C5NThe multi-channel acquisition system of MAX194, describes in detail the hardware and software design between MAX194, CPLD and DSP, the system has been successfully applied in the embedded measurement control system that the author participated in.
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