With the development of digital signal processing chip DSP technology, the speed of signal processing is getting faster and the capacity is getting larger and larger. In order to cooperate with the data transmission between different clock domains, FIFO must be used to achieve the purpose of data matching, so as to improve the system performance.

1 Overall design of the system

The system is mainly composed of signal acquisition circuit AD, FIFO, CPLD and digital signal processing chip TMS320C25409 of TI Company. It can collect 32 analog quantities and 64 switch quantities. The received analog signal must first be amplified and sampled by the operational amplifier, and then through the analog electronic switch, and then realize A/D conversion. The converted data is sent to the DSP for processing through the FIFO, and the CPLD is responsible for controlling data acquisition, A/D conversion and data reading. write timing. The block diagram of the system structure is shown in Figure 1.

Two high-speed A/D conversion chips AD976 are used in the system. AD976 is an analog-to-digital converter produced by AD Company. It is a successive approximation analog-to-digital converter using charge redistribution technology. FIFO selects IDT7202 from IDT Company. It has two sets of input and output data lines, independent read/write address pointers, sequentially read/write data from dual-port FIFO under the control of read/write pulses, and read/write address pointers start from the first storage unit, until the last storage unit, and then back to the first storage unit. The system uses 2 pieces of IDT7202 to expand the data width to 16 bits, DO~D1 are 64-channel switch data; D2-D15 are 32-channel analog data. When the system is working, the arbitration circuit inside the IDT7202 compares the read pointer and the write pointer, and accordingly gives the FIFO empty (EF) and full (FF) status indications; CPLD can control the FIFO reading according to the obtained FIFO status flag. /Write timing, to realize the read/write operation to the FIFO.

2 Introduction of FIFO chip IDT7202

FIFO (First In First Out) simply means first in first out. As a new type of large-scale integrated circuit, FIFO chip has been widely used in high-speed data acquisition, high-speed data processing, high-speed data transmission and multi-computer processing systems due to its flexible, convenient and efficient characteristics. IDT7202 is a high-speed, low-power, dual-port memory, with 9-bit data input and output, the chip capacity is 1K × 9 b, the input/output ports are controlled by a separate clock and enable signal, with “empty”, “” full”, “half full” and “almost empty, almost full” signs. The 9-bit input/output ports of the IDT7202 are controlled by separate clocks and enable signals. The input port is controlled by the write enable signal (W). When the write enable W is low, data is continuously written into the FIFO memory. Likewise, the output ports are controlled by a read enable signal (R) and have an output enable pin (OE). IDT7202 also has a reset terminal (RS), when RS is low, all flag bits of IDT7202 return to the original state.

3 FIFO and CPLD interface design

ATERA’s programmable logic devices support a variety of I/O level standards, including LVTTL and LVCMOS levels of 3.3 V, 2.5 V and 1.8 V. Since the FIFO must be powered by 5 V, when the CPLD reads the data from the FIFO to the internal memory, it needs to go through a level conversion chip. The system selects SN74LVCl*5A 16-bit bus transceiver with tri-state output, which supports bidirectional transmission of 8/16-bit data.

In the design of FIFO and CPLD data communication interface, CPLD mainly outputs control timing to reset, write and read ports of IDT7202, realize the storage of A/D conversion data to FIFO, and read data from FIFO into the internal memory of CPLD. Once the CPLD detects that the “BUSY” signals of the two AD976s are all high, and the delay is satisfied, the CPLD makes the write signal “W” of the FIFO output low, allowing data to be written to the FIFO. At the same time, the full flag signal FF of the FIFO is detected. If the signal is low, it means that the FIFO is full. At this time, the CPLD outputs the read timing to the FIFO, reads data from the FIFO, and detects the empty flag signal EF of the FIFO. If the signal is low, it means that there is data in the FIFO. It has been read empty, and data is not allowed to be read unless there is more data to be written. Two pieces of IDT7202 are used in this system, their reset, write and read ports are connected together respectively, and the data is read and written at the same time. Data DO-D8 are output from the first slice, D9-D15 are output from the second slice, and the two empty data bits of D16 and D17 are grounded. DO~D1 are 64-channel switching data, 64-channel switching data are latched by 8 pieces of 8D latches 74LS373 and directly sent to CPLD, and the switching value sampling sequence and the number of channels are judged by CPLD.

The asynchronous read and write operation sequence of IDT7202 is shown in Figure 2, and the description of each parameter is shown in Table 1.

4 FIFO and AD976 interface design

This system can connect up to 32 analog quantity, need to use two pieces of AD976 chip, the 16-bit data after conversion is sent into two FIFOs respectively. When the “BUSY” signal in any one of the two AD976s is low, the analog-to-digital conversion is performed. Only when “BUSY” is high, the data can be written into the FIFO, but whether the data is written into the FIFO It is determined by the write enable signal of the FIFO. When the write enable signal is valid from the CPLD, the converted data can be stored in the FIFO. There is a certain phase difference between the output of the A/D conversion data and the conversion clock. In the CPLD, the establishment time and the holding time can be satisfied by the delay or the clock manager, so as to ensure that the data is transmitted to the FIFO without missing codes. Both FIFO and AD976 use 5 V power supply, so the data line can be directly connected. In order to reduce the external interference to the data line, a small resistor of 100-200 Ω is connected in series between the data lines.

5 Conclusion

A design method of FIFO in a multi-channel data acquisition system is systematically introduced. The system can collect 32 analog quantities and 64 switch quantities. The system has the advantages of strong anti-interference, high reliability and low loss rate. The system can be used in equipment with a large amount of collection, and has been widely used in power fault monitoring devices.

Responsible editor: gt

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