This paper presents an intelligent bus interface design scheme based on DSP embedded enhanced can controller (ECAN) module. The design innovatively uses the latest adm3053 chip released by Adi company as the ECAN interface driver, which integrates can transceiver, signal isolation and DC / DC power supply isolation, achieving the purpose of interface miniaturization, low power consumption and low cost. The system architecture of ECAN module and the hardware circuit of bus interface are given. In terms of software design, it focuses on the internal register and mailbox structure of ECAN module, gives the software initialization, message sending and message receiving process, and finally gives the processing method of CAN bus message overload. The test results show that the intelligent bus interface module works stably and has good signal quality, which meets the needs of industrial control.
Can bus has been widely used in automobile, machinery and other industrial control fields because of its advantages of reliability, real-time and low cost. TMS320F2812 is ti’s most representative fixed-point DSP chip with low cost, low power consumption and high performance. It has powerful event management ability and embedded control ability. The embedded enhanced can bus controller (ECAN) module is fully compatible with can 2.0B protocol. The number of mailbox is increased to 32, and the functions of time stamp, message filtering and timeout sending are added to improve the flexibility of CAN communication application.
Adm3053 is a can transceiver integrated with signal and power isolation function launched by Adi in 2011. In this paper, TMS320F2812 and adm3053 integrated with ECAN module are used to design can node. In this design, the DSP embedded with ECAN module is used as the main controller of the node, and adm3053 chip is used to effectively replace the traditional can transceiver, signal isolation and power supply isolation circuits, which effectively realizes the miniaturization, low power consumption and low cost of the module.
The interface module can realize the normal can communication, and the communication control is more flexible. The data packet, level characteristics and eye diagram of the interface are analyzed by can communication monitoring card and special oscilloscope, and the results show that the signal quality is good.
1 Hardware Design
1.1 hardware system design
The hardware principle block diagram of CAN bus interface module in typical industrial control is shown in Figure 1, which is composed of intelligent processor, can protocol controller, signal isolation, transceiver and power supply isolation. The intelligent processor is responsible for receiving and sending bus data, analyzing and managing can protocol data, responding to PC commands and feedback interface health status; The function of CAN bus controller is to realize the function of data link layer, including bit timing logic, error management logic, acceptance filter, transceiver buffer management, etc; The function of CAN bus transceiver is to realize the function of physical layer, mainly the mutual conversion between receiving and transmitting signals and bus differential level; The isolation circuit consists of signal isolation and power isolation to achieve complete electrical isolation between the controller and transceiver.
The traditional CAN bus interface circuit is built by using independent interface management CPU, can controller, transceiver and isolation circuit. This method takes up a large board area, the interface logic is complex and the cost is high. This design applies the adm3053 chip newly released by Adi company, which integrates three functions of can transceiver, signal isolation and power supply isolation, as shown in the dotted box in Figure 1. Adm3053 has the following advantages
(1) Low power consumption and small size. The patent technology of icouple signal isolation based on the principle of electromagnetic isolation is adopted. The power consumption is equivalent to 1 / 10 of the traditional photoelectric isolator under the same data transmission rate. At the same time, the chip level voltage transformation technology isopower based on high frequency switch is used to realize power supply isolation. Create a completely isolated interface between CAN protocol controller and physical layer bus. It reduces the number of components, saves the circuit space, simplifies the interface design and reduces the design complexity;
(2) Higher performance. It is superior to the traditional photoelectric isolator in timing accuracy, transient common mode suppression and channel matching performance（ 3) The product cost is lower. The cost of each channel is equivalent to 40% of the traditional photoelectric isolator
1.2 ECAN module structure
The interface and structure circuit of ECAN are shown in Figure 2. ECAN has a 32-bit internal structure, including protocol kernel (CPK) and message controller.
After the protocol kernel CPK receives a message from the bus, the receiving control unit in the message controller determines whether to store the received message in one of the 32 message mailbox ram. The receiving control unit determines the location of the mailbox by checking the status of the message, the identifier and the shielding of the message object. The received messages are filtered and stored in the first mailbox. If the receiving control unit cannot find any mailbox to store the received message, the message is discarded.
A message consists of 11 bits or 29 bits of identifier, a control field and up to 8 bytes of data. When a message is sent, the message controller sends the message to the send buffer of CPK to start sending the message when the next bus is idle. When more than one message is to be sent, the message with the highest priority will be sent to CPK by the message controller. If the priority of two messages is the same, the mailbox with large sequence number will be sent first.
1.3 interface circuit design
The interface management CPU used in this paper is TMS320F2812, which uses its internal integrated ECAN module, so it only needs to connect the CAN bus transceiver module and isolation device to realize the CAN bus interface function.
The circuit diagram of ECAN interface is shown in Figure 3.
The left side of adm3053 is the logic terminal, and the pin wiring of the logic terminal is as follows:
(1) RXD and TXD are connected to ecanrx and ecantx pins of DSP respectively;
(2) The VCC is connected to the logic terminal VCC (+ 5 V) power supply;
(3) Vio is connected to IO power supply voltage vio of DSP;
(4) GND pin connected to logic terminal and ground terminal GND_ LOG.
The right side of adm3053 is the bus terminal, and the pin wiring of the bus terminal is as follows:
(1) Canh and canl are connected with can physical bus, and the two ends of the bus are connected in parallel Ω Termination resistance;
(2) The bus terminal voltage input is visoin, the isolation voltage output is vi-sout, and is grounded through the filter capacitor（ 3) Canh and canl connect the common mode inductor act45b-510-2p to filter the common mode signal on the bus;
(4) Canh and canl are connected in parallel with TVs pesd1can as transient suppression protection to prevent transient interference on the bus.
2 software design
2.1 ECAN memory mapping ECAN registers are mapped to the peripheral frame 1 area of on-chip memory. CPU uses these registers to configure and control can message objects. Control and status registers only allow 32-bit access. ECAN provides 32 message mailbox, each mailbox can be configured to send or receive mailbox. The message is a RAM area, which is mapped to the RAM memory of DSP. The address allocation of each mailbox ram is shown in Figure 4. The message mailbox is used to store the received can messages or can messages waiting to be sent. When the mailbox is not used to store can messages, the CPU can use the RAM space of the message mailbox as general memory. The register and message RAM space of ECAN module is shown in Figure 4.
2.2 communication software
2.2.1 system initialization
ECAN module initialization can only be carried out in initialization mode. The conversion between initialization mode and normal operation mode is realized through can network synchronization. In other words, before changing the mode, can controller needs to detect the bus idle state (equal to 11 receiving bits). If there is a dominating bus error, can controller will not be able to detect the bus idle state, Therefore, mode switching cannot be completed. Setting CCR register to 1 makes can module work in initialization mode, and only when CCE register is set to 1 can initialization be performed. After the above settings are completed, the ECAN module configuration register can be operated. The initialization process of ECAN module is shown in Figure 5.
2.2.2 message sending
According to the initial configuration of the system, the data to be sent is written into the data area of the corresponding message mailbox of the ECAN module. Here, we need to pay attention to the setting of the dbo register of the data byte order. When dbo = 0, data reading and writing starts from the least significant bit of can-mdl register and ends at the most significant bit of canmdh register. When dbo = 1, data reading and writing starts from the most significant bit of canmdl register and ends at the least significant bit of canmdh register. Set send command word cantrs. N = 1, start sending operation, ECAN module will automatically set response command word Canta. N = 1. Finally, manually clear send command word and response command word. The message sending process is shown in Figure 6.
2.2.3 message reception
According to the initial configuration of the system, when the ECAN module receives the message on the bus from the mailbox, the corresponding receive message waiting register can-rmp. N is set. At this time, the CPU should check the message discarding flag register RML. If RML is 1, the message in the mailbox has been covered, and the CPU can choose to request retransmission to the source node. The receiving process ends.
When RML is 0, CPU can read data from mailbox data area, clear RMP. N at the same time, and then enter the state of waiting to receive (RMP = 0, RML = 0).
The message receiving process is shown in Figure 7.
2.2.4 overload treatment
If the speed of CPU can’t process important messages quickly, and message overload occurs, this situation can be solved by adding backup mailbox, that is, configuring multiple mailbox with the same identifier. For ECAN module, each message object has its own mask Lam (n). In order to ensure that the message will not be lost, the OPC flag position of the backup message object will be covered to prevent the unread message from being covered. If the ECAN module needs to store the received message, check the backup mailbox first. If the backup mailbox is empty, store the message. If the RMP flag of the backup mailbox is set, the message is not read. Because the backup mailbox data cannot be covered, the message data is stored in the original mailbox, and an interrupt generated at this time can be used to read the important data of the backup mailbox.
The can intelligent bus interface module designed in this paper is tested by multi node transceiver in physical environment. The results show that the hardware circuit works stably and the data transceiver function is normal. The bus level characteristics and eye diagram are shown in Figure 8.
It can be seen from figure 8 that the bus signal (canh, canl) is regular, the signal waveform after differential is smooth, and the eye diagram shows that the interface communication quality is good.
The application of adm3053 chip can effectively reduce the area of circuit board, conform to the principle of miniaturization, and effectively reduce the cost of CAN bus interface module, which has a broad application prospect.