With the continuous improvement of people’s requirements for real-time signal processing and the rapid development of large-scale integrated circuits, DSP chip, as the core and symbol of digital signal processing, has been developed and applied rapidly. It can not only be widely used in communication system, graphics / image processing, radar sonar, medical signal processing and other real-time signal processing fields. As far as ADI company is concerned, following the 16 bit fixed-point adsp21xx and 32-bit floating-point adsp21xxx series, it recently launched the new TigerSHARC series devices. This paper introduces the design of an image acquisition and processing system based on ADSP-TS201S.

Overall scheme of the system

The system can complete the image acquisition, processing and display, so as to realize the intelligent signal processing of target recognition and tracking. The system collects the digital and analog video data of the camera and displays them on the PC through PCI bus. The whole system is mainly composed of video signal acquisition module, DSP image processing module and PCI interface module (Fig. 1).

Design of image acquisition and processing system based on DSP chip

Figure 1 block diagram of image acquisition and processing system

The circuit design of each function module of the system

·Video signal acquisition module

The camera provides two video signals: one is analog video and the other is digital video.

After clamping correction and amplification, the analog video signal is sent to the A / D converter, and then the video signal is sent to DSP1 after being locked by FPGA; through the video synchronization separation circuit, the line and field synchronization signals of the analog video are separated by LM1881, which is used to control the video data acquisition to DSP1 for image processing. The clamp correction and video synchronization circuit is shown in Figure 2. The analog video is input by the operational amplifier, and the center level is adjusted to 3.3V, which is added to the A / D input terminal. The data after a / D conversion is locked in FPGA. AD8047AR of ADI company is used for operational amplifier, ad9050 of ADI company is used for a / D converter. Ad9050 is a 10 bit a / D converter, and the high 8 bits of ad9050 are used in FPGA. The sampling clock is 12Mhz, which is the same as the digital video signal. The 48mhz clock is generated by FPGA.

Figure 2 analog video input conversion circuit

The digital video signals of the camera are 14 pairs of differential signals, which are converted into single ended signals by FPGA, and the data is locked. Each pixel is 14 bits, and each frame is 320 × 240.

·DSP processor module

The DSP processor array module is mainly composed of four high-speed and high-performance DSP processing chips ADSP-TS201S. The performance of ADSP-TS201S is as follows:

The basic performance indexes are as follows:

When the speed is 600MHz, the core instruction cycle is 1.67ns

24mbits on-chip DRAM, divided into 6 4mbits blocks (128kwordsx32bits)

On chip dual operation modules, each containing an ALU, a multiplier, a shifter and a register group

Dual integer Alu provides data addressing and pointer operation functions

The chip provides 14 channel DMA, external port, 4 chain junctions, SDRAM controller, programmable mark pin and 2 timers

The arbitration system on chip can realize the seamless connection of 8 tigersharcdsps

There are three independent 128 bit buses inside

External data bus 64 bits, address bus 32 bits

4.8 billion 40 bit MAC operations per second or 1.2 billion 80 bit MAC operations per second; 1024 point complex FFT (base 2) time 15.7us

External port 1g bytes per second; chain junction (each) 1g bytes per second

DSP processor array module DSP1 is used to sort out the collected video signal, and after the corresponding preprocessing, the data will be sent to the following DSP for further processing.

DSP1 parallel port should be connected with FPGA output video data and flash to complete DSP loading. Irq0 and IRQ1 of DSP1 are used as frame interrupt and line interrupt of video input respectively, and are connected to FPGA. The connection circuit is shown in Figure 3 below.

Am29lv017d of AMD company is selected as flash memory, which is 2mx8 bit memory. Flash can be programmed through DSP1. When reading and writing flash, the data output bus d0 ~ D13 of FPGA should be high resistance. Otherwise, when the data channel is running, the flash output should be high resistance, so BMS is used to select flash.

Figure 3 connection diagram of DSP1, FPGA and flash

Dsp2 and dsp3 are the main algorithms in image processing. Dsp2 and dsp3 are respectively connected with DSP1 through the chain intersection to receive the data transmitted by DSP1. Dsp2 and dsp3 are also connected with dsp4 through the chain intersection to transmit the processed data to dsp4 for further processing and data collation. In addition, dsp2 and dsp3 are directly connected by the chain junction to realize the channel between dsp2 and dsp3, so that dsp2 and dsp3 can be easily configured into pipeline or parallel processing mode.

Dsp4 in DSP processor array module receives the data from dsp2 and dsp3. After further processing, it sends the final processed data to dual port RAM through data bus, and sends the data to PC through PCI interface chip PCI9054. The dual port RAM adopts three pieces of idt70lv27 (32kx16 bit) to form 96kx16 bit mode, which guarantees to write one frame at a time (320 × 240 pixels, two bytes per pixel). When dsp4 writes one frame of image data, it will interrupt the PC and request the PC to read the data away. When the PC reads one frame of image data, it should provide the corresponding response to allow dsp4 to refresh the dual port RAM. The interconnection circuit of DSP array is shown in Figure 1, and the connection between dsp4 and dual port RAM is shown in Figure 4. Dsp4 is connected with three pieces of dual port RAM to form an interface with PCI9054. The flag0 of dsp4 is used as the video transmission handshake signal output through PCI9054.

ADSP-TS201S array machine adopts the way of chain intersection interconnection, and sets the data transmission in the main data transmission direction to start the flag signal to the IRQ of the receiver to generate the interrupt, so as to better realize the timing matching.

DSP1 introduces the work / close selection (flag1 input), and the data mode (digital / analog) selection is read in by the data14 pin. The data selection mode can be read once when a frame of data is input, and then it can not be processed any more.

Figure 4 interface between dsp4 and dual port RAM

·PCI interface module

PCI interface adopts PCI9054 interface chip of PLX company, 32 bits, 33MHz data bus. Ram1, 2 and 3 dual port RAM (idt70lv27) are used as dsp4 data output buffer. Read into PC by PCI9054. In the dual port RAM, it is equivalent to the right half interface, PCI9054, and its circuit connection is shown in Figure 5. PCI9054 corresponds to the signal of PCI slot. It is connected according to the name of PCI slot. 93cs66 is selected to load EEPROM. When LD0 ~ ld3 is introduced into FPGA, it can output 4-bit status in single I / O mode for host control. On and off, digital video / analog video selection takes one of a16-17 decoding as address selection. After FPGA read in, decode into control signal output.

Figure 5 connection of PCI9054 with dual port RAM and FPGA

epilogue

The image acquisition and processing system based on ADSP-TS201S can achieve high-speed image processing, real-time image display and target tracking. In practical application, the system works stably and achieves the desired effect.

Editor in charge: GT

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