In the field of digital video recording and digital monitoring, people are usually only interested in the movement of objects in the scene. In this case, it is necessary to preprocess the input video signal to identify whether there is object movement in the scene, that is, motion detection, and then decide whether to do further processing, such as video recording, alarm, etc. For the video system, through motion detection, it can avoid unnecessary digital video recording, effectively reduce the storage space required by the system; at the same time, it can speed up the retrieval speed and improve the effectiveness of the data. For monitoring system, motion detection is an effective way to monitor scene information.
1. Schematic diagram of controller
The design and implementation of controller CPLD is the core part of motion detection. It needs to control and process peripheral devices. In this paper, Altera’s CPLD epm7128s84-15 is selected and VHDL is used as hardware description language. However, the VHDL source code is suitable for both CPLD and FPGA devices. The design block diagram of CPLD controller is shown in Figure 1.1. The overall structure of the controller can be divided into three parts: image acquisition control module, SRAM read / write control module and control comparison module.
Fig1.1 System diagram
Figure 1.1 system principle block diagram
Image acquisition and control hardware part
SAA7111A, a video A / D conversion chip of Philips company, is selected for image acquisition. SAA7111A is a powerful video signal preprocessing chip launched by Philips company. The most basic function is analog to digital conversion. The output is digital video signal with aspect ratio of 4:3 and 16:9, which conforms to ITU 601 standard. In China, the digital TV signal with 4:2:2 sampling format, PAL system and 4:3 aspect ratio is usually used.
The CPLD used in this paper is EPM7128SLC84-15 of Altera company. It has 128 macro cells and 7.5ns delay. SRAM chip is is61c1024l-12 of ISSI company. Its capacity is 128K × 8bit and has 10ns delay. After CPLD detects the movement, ime6400 is required to further process the signal by interrupt. The system structure diagram is shown in Figure 1.1.
SAA7111A outputs digital video signals with aspect ratio of 4:3 and 16:9. The output signal includes the blanking period. 625 lines are scanned in each frame, and 864 pixels are sampled in each line. Therefore, the total resolution is 864 × 625. A frame of data is divided into two odd and even fields. From 624 lines of the previous frame to 310 lines of this frame, the odd field blanking period is from 624 lines of the previous frame to 22 lines of this frame, and the odd field effective lines are from 23 lines to 310 lines; from 311 to 623 lines of this frame, 311 to 335 lines are even field blanking periods, and 336 to 623 lines are even field valid lines.
In the acquisition process of a frame of image data, the most important thing is to judge the start and end time of a frame of image data. Based on the study of the timing relationship of synchronous signal (rts0, VREF and href) provided by SAA7111A, the start and end points of acquisition process are precisely controlled by state machine. The rising edge of rts0 signal marks the starting point of a new image. VREF signal is the effective pixel line period during forward scanning of high-level field image. During the effective pixel row period, href signal is the effective sampling time of high-level corresponding pixel. Only one frame of sampled data is cached. When sampling the second frame of data, the cache data corresponding to the sampled data in the first frame is read and compared. A counter is used to record the comparison result. If the difference exceeds the threshold value, the counter will be increased by one, otherwise it will not be added. When the count value exceeds a specified value, it is considered that there is object movement in the input video data. The advantage of this is that the required buffer is small, and CPLD can process the data separately, which improves the independence of the motion detection module, and the motion detection module can be debugged separately.
3. Image acquisition and control software
The reference signal sequence of SAA7111A output in PAL system is shown in Figure 1.2. LLC is the pixel clock signal with the clock frequency of 27MHz, and the high level represents the output of one pixel; HS is the line synchronization signal, and its rising edge indicates the beginning of the line blanking period, and the down hop indicates that a new line of sampling data is about to start; vs is the field synchronization signal, whose rising edge indicates the beginning of the field blanking period, and the down hop indicates that a new field sampling data is about to start; rts0 is the odd and even field mark When rts0 is high level, it outputs odd field sampling data, while rts0 is low level, even field sampling data is output.
Fig1.2 SAA7111A timing diagram
Figure 1.2 sequence diagram of reference signal output from SAA7111A
The initial settings of SAA7111A in the system are as follows: one analog video signal input, automatic gain control, 625 line 50 Hz pal mode, yuv4:2:2 (16bit) digital video signal output, and setting the default image contrast, brightness and saturation.
The main function of the read / write control module is to control the reading and writing of SRAM. The following is a part of VHDL program to realize the above process.
Sram_ write_ control process store_ field valid spclk2 line_ counter
wriTIng《=valid and spclk2 and spclk and store_ field and line_ counter0
Sram_ read_ control process compare_ field valid spclk2 line_ counter
reading《=valid and compare_ field and spclk2 and line_ counter0
These two processes are used to control the read-write signals of SRAM. Reading and writing are just in inverse phase with the read-write signals of SRAM. The valid variable indicates whether the current input line is a valid line to be sampled, spclk is the pixel data synchronization pulse, and spclk2 is its bispectrum, which is used to indicate whether the current input data is the luminance component y. line_ Counter 0 = 1 indicates an odd number of rows. Store_ Field and compare_ Field indicates whether the field data needs to be saved or compared.
update_ data_ bus process store_ field valid ccd_ data
if store_ field=’1’and valid=’1’then
data_ sram《=ccd_ data
compare_ The data process compares the data sampled before and after the sampling interval (when the input is chrominance component CR or CB). If the comparison result exceeds the allowable value, the counter pixels is increased by 1, otherwise it is not added.
moTIon_ detect process pixels
if pixels》max_ pixels then
max_ Pixels is a threshold that represents the maximum number of unequal samples allowed in a frame of data when the counter pixels exceeds max_ When pixels is used, it is considered that the object movement is detected. CPLD sets the INT0 output pin high and requests interrupt from the processor. Here max_ Pixels takes 600, which can set the appropriate value as needed.
Of course, this detection method itself has its own shortcomings, the most important point is that the actual detection is only the change of light brightness in front of the camera, which can not intelligently determine the cause of this change, nor can it distinguish the shape of moving objects. On the other hand, from the experimental results, sometimes there will be misjudgment; when the moving object is far away from the camera, the detection sensitivity will also be reduced, resulting in missed judgment. Misjudgment and missed judgment are a pair of contradictions. In practical application, it is necessary to debug repeatedly according to the actual situation to select the best threshold to reduce the occurrence of these two situations.
The author’s innovation is to design an image acquisition and processing controller based on CPLD / FPGA chip epm7128s84-15. At present, the design is being used in the security monitoring system of our hospital, and the effect is good.
Editor in charge: GT