With the rapid development of science and technology, the application of automatic control system in various fields is more and more, especially the computer automatic control system has become an indispensable part of modern science and technology, military engineering and modern industry. Therefore, automatic control elements such as various motors and generators used as power devices and various control motors used as signal conversion are widely used in various control systems. To control the controlled object, not only the controller and actuator, but also the feedback device is needed. Therefore, the encoder as a motor angle, speed, direction detection device, has also been widely used. The encoder includes resolver, Hall sensor and photoelectric encoder. Among them, photoelectric encoder has high precision, strong anti-interference ability, simple interface and convenient use, so it has been widely used.

The former has the advantages of high resolution, low price, simple interface and so on. However, in today’s industry, the memory function without power failure has constituted a great limitation to its application; The latter has compact structure, small volume, digital interface, strong anti-interference ability and power-off memory function, so it has been paid more and more attention in application.

In the current market, Heidenhain has a wide range of products with good quality assurance, which are widely used in machine tools, automation fields, especially in semiconductor and electronic manufacturing industries. Heidenhain photoelectric encoder occupies a large market share, and the corresponding decoding equipment is not suitable for embedded system applications. In this paper, according to the Heidenhain encoder used in the experimental turntable, the general data processing modules of incremental and absolute are designed. The module has the advantages of fast signal processing speed, high precision, accurate data, flexible application, convenient use and debugging, low cost and so on, which can meet the needs of use.

1 overview of Heidenhain encoder

1.1 high precision incremental encoder

The incremental encoder converts the displacement into periodic electrical signal through grating, and then converts the electrical signal into counting pulse. The displacement is expressed by the number of pulses. The grating is composed of periodic lines, and the position information is obtained by calculating the increment from a certain point (the number of measurement steps). The grating of the high-precision Heidenhain incremental encoder to be measured by this module also has a track engraved with the distance coding reference point, which speeds up the reference point to return to zero. Figure 1 below shows a circular grating with distance coding.

Design of encoder Application module based on Xilinx FPGA platform and TI DSP platform

Figure 1 circular grating with distance coded reference point (era4480)

These reference points are separated from each other by a distance determined by mathematical algorithm. After two pulses of three reference points have passed, the follow-up electronic equipment can find the absolute reference point.

1.2 high precision absolute encoder

Absolute encoder uses natural binary, cyclic binary (gray code) or PRC code to conduct photoelectric conversion on the physical reticle on the code disk, converts the rotation angle of the connecting shaft into the corresponding electric pulse sequence, and outputs it as digital quantity. Each position corresponds to a certain unique digital code, so it has the power-off memory function.

Sometimes, the digital drive system and feedback loop that get the position value through the position encoder also need the encoder to provide some additional value. In order to make the system more reliable, the encoder should also have the function of error detection and diagnosis. Endat2.2 data interface of Heidenhain company is a bidirectional data interface suitable for encoder. It can transmit the position value of absolute or incremental encoder, and can also transmit or update the information stored in encoder or save new information. Because of the serial data transmission mode, it only needs 4 lines. The data transmission is synchronized with the clock signal of the subsequent electronic equipment. The transmitted data type (position value, parameter or diagnostic information, etc.) is selected by the mode command sent to the encoder by the subsequent electronic equipment.

2. Hardware design

This module uses the combination of DSP and FPGA. DSP is mainly used in the field of digital signal processing, which is very suitable for high-density, repetitive operation and large data capacity signal processing. On the one hand, FPGA / CPLD device can achieve parallel work on hardware, which is very suitable for real-time measurement and control and high-speed applications. On the other hand, the physical mechanism is as reliable as pure hardware circuit, especially anti strong electromagnetic interference. The combination of the two can realize broadband signal processing with high speed and good reliability.

According to the functional requirements of the scheme, the structure diagram of the design module is shown in Figure 2

Design of encoder Application module based on Xilinx FPGA platform and TI DSP platform

Figure 2 hardware structure diagram

In the figure, the module connector is a standard DB15 connector. Through pin configuration, it can communicate with incremental encoder and absolute encoder with endat2.2 interface. The transceiver unit of the module supports RS-485, and the differential signal and single terminal signal are converted through the interface chip. In order to improve the measurement accuracy of high-precision incremental encoder data, it is necessary to install four reading heads on the same incremental encoder, measure the incremental encoder data respectively, and then synthesize the position value. In this way, there are four interfaces on the board to read the encoder signal.

Xc3s700an of spartan-3an series of Xilinx company is selected as FPGA chip, and the logic cells are 10476.

Implementation: ① count the incremental signal and collect the reference signal, clear the incremental signal after counting the data of reference channel; ② collect the position signal of endat2.2 absolute encoder; ③ save the count processing before the rising edge of external synchronous clock, store the data in dual port RAM, waiting for DSP to read.

The DSP chip of this module is TMS320F28335 of TI company, and the main frequency can reach 150MHz. TMS320F28335 adds floating-point operation unit, which can save code execution time and storage space while maintaining the advantages of the original DSP chip, such as powerful control and signal processing ability, C language programming efficiency and so on. F28335 is connected with xc3s700an through GPIO port. It has 4 address lines and 16 data lines, and can accept 16 kinds of encoder signals. The DSP part of the module opens up the parameter storage area, reads the data in FPGA when the interrupt signal arrives, completes the data synthesis, and sends the data to the main control chassis through SCI serial port, and the electrical form is RS422.

The module board is powered by 5V power supply. 3 software design and Implementation

According to the hardware architecture, the software functions of DSP and FPGA are analyzed and programmed.

FPGA part uses ise10.1 development software of Xilinx company, adopts Verilog language, receives the encoder signal input from the interface pin, and correspondingly realizes the TTL pulse count and reference signal generation after the output of Heidenhain high-precision incremental encoder is subdivided by subdivision box, or communicates with endat2.2 of absolute encoder. Ccs5.2 of TI company is used in the development software of DSP, and C language is used for programming. DSP completes the final position synthesis processing of the signal. Here, we first define the relevant parameters of the encoder, such as the total number of encoder engravings, resolution, the reference number of incremental encoder with reference channel, the fraction of incremental signal before entering the FPGA (depending on ibv600), and whether the FPGA quadruples the TTL count. When using, modify the parameters according to the specific encoder type.

The software can read the position value of high-precision incremental encoder and absolute encoder. The following will be introduced respectively.

3.1 measuring incremental encoder position value

3.1.1 FPGA design of related parts

Incremental encoder is a rotary photoelectric encoder, which outputs a series of pulses according to the rotation angle of the shaft. Generally speaking, the encoder output has three-phase signals: A, B, Z. A. B phase signal is a quadrature square wave pulse train with phase difference of 90 degrees, each pulse represents a certain angle of rotation of the measured object, and the phase relationship between a and B reflects the rotation direction of the measured object, that is, when a phase is ahead of B phase, the rotation direction is forward; when B phase is ahead of a phase, the rotation direction is reverse. Z signal is a pulse signal representing the reference code channel, which can be used for zeroing and alignment. When the object rotates at a certain angle, the pulses of a and B change, and the angular displacement is calculated according to the direction of AB phase change and the number of pulses. When AB phase changes to 00 10 11 01 00, it is to output forward counting pulse, pulse count P Plus 1; when AB phase changes to 00 01 11 10 00, it is to output reverse counting pulse, pulse count P minus 1. Phase change several times, count operation several times. It should be pointed out that only when the state of phase changes in strict accordance with the above 8 ways, the FPGA can count. When programming in Verilog, the former AB phase level state and the latter AB phase level state can be formed into a scattered address vector, and then the vector can be used as a conditional statement for counting operation. For example, when AB changes from 00 to 10, the vector is 0010, P = P + 1. Conversely, if AB goes from 10 to 00, the vector is 1000, P = P-1. The following is the Verilog code for FPGA to read TTL data and form the scatter address vector:

always @(posedgeinClk)


Regua1a2state = {inincua1, inincua2}; / / read AB vector

if(regUa1a2State! =Regallstate [1:0] / / state change


Regallstate = {regallstate [1:0], regua1a2state}; / / compose a new hash address vector

regPulseStateChanged《= 1;



regPulseStateChanged《= 0;



In addition, the incremental encoder has no power-off memory function, and the zero position must be determined every time it is started. In the past, when there was only one zero reference point, sometimes it was necessary to turn 360 ° Z phase to produce a pulse to determine the zero position. There are several distance coding reference points in the reference point channel of high precision Heidenhain encoder. When any reference point passes through the reading head, the Z phase outputs pulse. At this time, the previous pulse count P needs to be saved (recorded as Q), and P is cleared. In this way, every time the Z phase outputs pulses, the value of P is the number of pulses after the last reference point, which is an important basis for DSP to determine the zero position and the current reference point.

FPGA measures four groups of information of four reading heads, writes it into dual port, and waits for DSP to read it. There are two data written into each group: ① refpulsecnt (Q value) of count increment when passing the reference channel last time, ② pulsecnt (P value) of count increment.

3.1.2 DSP design of related parts

The reference angle of incremental encoder reference channel in DSP program is the number of pulses and angle corresponding to each distance coding reference point. Because the number of pulses (i.e. Q value) between each two reference points is different and unique, the nearest reference point can be determined according to the Q value in the read FPGA dual port, and then the angle of the reference point can be obtained by “looking up the table”. At the same time, the DSP reads the p value and multiplies it by the resolution to get the angle after the current reference point. The combined two can be added to determine the position value measured by the corresponding reading head. The resolution is 360 ° / total scale * before entering the FPGA, the number of subdivisions * 4 (the essence of TTL counting in FPGA of this module is to quadruple the frequency of AB channel signal). After all reading heads pass zero, the four reading head signals input to DSP have an absolute position relative to the zero point of reference channel. Generally speaking, when installing the reading head, the position of the four reading heads should be adjusted according to the position value of the single reading head. Generally, the difference of 90 degrees between two adjacent reading heads is the best. Taking any reading head as the reference, the absolute position difference of the other three reading heads relative to the reference reading head is 90 °, 180 ° and 270 °. In order to simplify, 1 of the input port of the circuit board is used as the reference. The synthetic position is a = (a1 + A2 + a3 + a4-90-180-270) / 4 = (a1 + A2 + a3 + a4-540 °) / 4. Due to the installation system error and the requirement of synthetic position value greater than 0, 520 ° can be used instead of 540 ° in calculation. Its range is (E, e + 359.9999), e is the error. At this time, 360 needs to be modulized, and the working range of the final composite value is (0359.9999). 3.2 measure the position value of absolute encoder

The module refers to the endat2.2 technical manual provided by Heidenhain company, and sets the parameters: according to the encoder bits and mode command, set the transmitted data bits_ tx_ oem_ value、ct_ rx_ oem_ Value; the number of additional information to be transmitted AI_ Count: transmission clock frequency parameter freq_ oem_ Value: the setting parameter freq of recovery time III (TST)_ tst_ Value, etc. The subfile of endat2.2 is measured, and the corresponding operation is carried out according to the parameter transformation state machine. In addition, the program has a cable transmission delay measurement module PDM. Then, according to the format shown in Figure 4 below, the signal D to be transmitted to the encoder is set according to the information demand_ in。 After the rising edge of the system clock arrives, start is immediately passed_ The trans signal control starts to communicate with the encoder. Receive the encoder data and read out the corresponding D_ The data representing the position value is obtained and written into the dual port.

Design of encoder Application module based on Xilinx FPGA platform and TI DSP platform

Figure 4 endat2.2 input data “d”_ in”

In the figure above, mode bits is a 6-bit mode instruction, and the most basic mode of encoder sending position value is 000111. The meaning of mode instruction and other parameters can be found in the technical manual.

DSP reads absolute signal data from FPGA dual port RAM, takes significant bits and multiplies the resolution of absolute encoder to get position information. The resolution is 360 ° / 2 ^ n, and N is the corresponding number of absolute encoder bits.

3.3 data output

The module communicates with the host computer through RS422 asynchronous serial interface, and the serial interface is realized through the SCI port of DSP. The designed module also needs the synchronous sampling frequency signal sent by the host computer, which is connected with DSP as the interrupt signal to start the ISR function. At the same time, the signal pin distributes the external synchronization clock to FPGA by skipping the pin. In this way, the clock source of the two is unified, and then the DSP can read the required data correctly by accessing the dual port of FPGA. The process sequence diagram is shown in Figure 5

Design of encoder Application module based on Xilinx FPGA platform and TI DSP platform

Fig. 5 overall process sequence diagram

As shown in the figure above, in t_ 1, the FPGA starts the communication with the encoder_ 2, the FPGA stores the incremental encoder pulse count or absolute encoder information into the dual port_ At 3:00, the rising edge of the external synchronous clock starts the DSP interrupt program, reads the data stored in the FPGA dual port and synthesizes the position value. After synthesizing the dimension, the absolute position value is transferred to the main control chassis through RS422 interface. In this way, the data obtained by the master is the data of the previous frame, that is, there is a frame delay. The larger the clock frequency is, the smaller the delay is. Therefore, the sampling frequency has certain requirements, not too low. 4 experiment and data analysis

After the module is designed, a platform needs to be built to check whether the function is realized. The experimental platform is shown in Figure 6

Design of encoder Application module based on Xilinx FPGA platform and TI DSP platform

Figure 6 experimental platform

As shown in Figure 6: turn on the power control switch, then load the DSP and FPGA programs into the f28335 and xc3s700an chips respectively through the emulator from the PC, and open the main control chassis. Finally, click the run key on CCS and toggle the encoder to observe the encoder position value in the variable observation window at the top right of CCS software interface. The interface is shown in Figure 7 below

Design of encoder Application module based on Xilinx FPGA platform and TI DSP platform

Fig. 7 CCS interface of observing position value during experiment

In this experiment, the 23 bit Heidenhain absolute encoder ecn1023 is used, and the external synchronous clock source is 500Hz. The internal frequency of FPGA is 10MHz, and the input frequency to endat2.2 is 64mhz. The position of the interface is 359.8117303848267 degrees. In the experiment, through the real time and automatic refresh function, it is also observed that the change of data on the interface is almost synchronous with the rotation of the encoder. After the encoder stops rotating, the data before the first three decimal places is very stable, and the data before the third, fourth and fifth decimal places are relatively stable. It can be seen that this module can meet a certain measurement speed and accuracy, and can work well.

After knowing the performance of the module through experiments, we need to test the accuracy. The module and the standard detector measure a Heidenhain absolute encoder at the same time, and measure 24 groups of positive and negative values in 360 degrees. Results: the positive RMS value was 0.67 arcsec, and the range was 1.9 arcsec; the negative RMS value was 0.76 arcsec, and the range was 2.2 arcsec. The two sets of error curves are shown in Figure 8 below

Design of encoder Application module based on Xilinx FPGA platform and TI DSP platform

Figure 8 two sets of error data curve of positive and negative detection

It can be seen from the figure that the 24 sets of data from 0 to 23 are all measured when they change from 0 to 36 degrees. As shown in the figure, the two groups of error curves are basically coincident, and a correction value can be added at the maximum error point to reduce the error.


Encoder is widely used. This paper introduces in detail a general and practical module for measuring the data of all kinds of Heidenhain encoders. The module is based on Xilinx FPGA platform and TI DSP platform, easy to use and debug, users can quickly master; through the experiment and precision detection, the design purpose is achieved, and the work is reliable; the module is small, can communicate with the host computer, and can be well integrated into the embedded system. At present, this module has been used in the data processing of incremental and absolute encoders used in the experimental turntable. It is intended to be integrated into the laboratory drive control cabinet. It is being further developed to measure and process the additional information of endat2.2.

Editor in charge: GT

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