An interconnection method between industrial fieldbus and Ethernet is proposed. The design and implementation of protocol conversion gateway between Ethernet and CAN fieldbus are introduced. AT89C55 is used as the main processor to realize the interconnection between CAN bus and Ethernet through two interface chips. Its hardware structure and software design idea are given respectively. It provides a feasible method for the integration of enterprise information network and control network.

 Ethernet interface module:The system selects AT89C55 single chip microcomputer produced by ATMEL company with high performance and price. It is oriented to measurement and control object and embedded application, so its architecture, CPU, instruction system and peripheral unit circuit are specially designed according to this requirement. It has up to 20 KB flash program memory inside. AT89C55 is fully compatible with 8051 instruction set. On chip flash facilitates users’ online programming. The working rate can be up to 33 MHz, 256 B internal RAM, 32 programmable I / O ports, 3 16 bit timing / counters and 8 medium cut-off sources. It supports low-power idle working mode. RTL8019AS chip is selected as Ethernet interface. It is a highly integrated Ethernet controller produced by Realtek company, which can realize all functions of Ethernet media access layer (MAC) and physical layer (PHY). There are two ram areas in RTL8019AS: one is 16 KB with addresses of 0x4000 ~ 0x7FFF. To receive and send data packets, you must read and write 16 KB ram in RTL8019AS through DMA. It is actually a dual port RAM, that is, there are two buses connected with it. One bus is used for RTL8019AS to read / write or write / read the ram, that is, local DMA; Another bus is used for MCU to read or write the ram, namely remote DMA; The second is 32 bytes, with addresses of 0x0000 ~ 0x001f, which is used to store Ethernet physical address. The hardware interface schematic diagram of the main control chip and Ethernet interface chip is shown in Figure 2. It is worth noting that the maximum packet size of Ethernet can exceed 1500 bytes, and the on-chip RAM of AT89C55 is only 256 bytes, so it is impossible to store such a large packet. Therefore, a 32 KB external RAM is expanded here, which can also improve the data transmission speed of MCU.

Design of embedded gateway circuit based on CAN bus and Ethernet

  Can interface module:The main components of can system are can controller and transceiver. In this design, SJA1000 chip and PCA82C250 chip are selected as can interface module. SJA1000 is an independent can controller. It is an alternative to another can controller pca82c200 of Philips company, and a new working mode (Peli can) is added, which supports can 2.0B protocol. SJA1000 mainly completes the communication protocol of can, realizes the assembly and splitting of messages, filtering and verification of received information, etc.

Design of embedded gateway circuit based on CAN bus and Ethernet

PCA82C250 is the interface between CAN controller and physical bus, which is mainly used to enhance the driving ability of the system. In the system using transceiver, the number of nodes can reach at least 110, and it also has the ability to reduce radio frequency interference (RFI) and strong anti electromagnetic interference (EMI). When dealing with this part of the circuit, there are several places to pay special attention to:

(1) Crystal oscillator circuit problems. 89c55 and SJA1000 should have their own independent crystal oscillator circuit, which can not use the clock output signal clkout of SJA1000 to drive the single chip microcomputer.

(2) Reset pin problem. Although the reset of SJA1000 is low level, it cannot be directly connected to the reset pin of MCU through a non gate. Generally, there are two ways to solve the problem of reset pin: the first is to use the I / O pin of single chip microcomputer to control the reset pin of SJA, which has the advantage that single chip microcomputer can completely control the reset process of SJA; The second is to use an appropriate reset chip. In order to reduce the cost, the design adopts the first method.

(3) The potential of rx1 pin must be maintained at about 0.5 VCC, otherwise the logic level required by CAN protocol cannot be formed.

(4) We must pay attention to the terminal impedance matching of the cable, which directly affects whether the CAN bus can work normally and the network performance. The hardware circuit diagram of the can interface module is shown in Figure 3. A slope resistance R is connected to the RS pin of PCA82C250, and the resistance can be adjusted appropriately according to the bus communication speed.

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