1 Introduction

The digital phase-locked loop frequency synthesizer has been widely used in the field of military and civil wireless communication, and the programmable large-scale digital phase-locked loop frequency synthesizer controlled by CPU is the key technology. At present, programmable logic circuits are developing rapidly in the design of digital systems. Many medium-scale and even large-scale digital systems can be integrated on a single chip through programmable logic circuits, that is, the design of the entire digital system is completed with one chip. Therefore, it has become possible to integrate the digital phase-locked loop frequency synthesis system controlled by CPU in a programmable logic chip. The system consists of multiple programmable digital frequency dividers, digital frequency discrimination-phase discriminators and a CPU that coordinates and controls the work.

2 System structure

The working principle of the digital phase-locked loop frequency synthesis system is: the phase-locked loop accurately locks the high-stability reference frequency (usually provided by the crystal oscillator directly or after frequency division), and the programmable frequency divider is connected in series in the loop. , change the frequency division ratio of the frequency divider by programming, so that the total frequency division ratio of the loop is N (which can be changed by programming), so that the loop can output N times the reference frequency stably, and the control of the whole program and system is to done by the CPU.

Fig. 1 is the FPGA realization scheme of the digital phase-locked loop frequency synthesis system controlled by CPU.

The dotted line part in Figure 1 is the CPU module. The CPU completes the system control by reading the ROM and setting the corresponding registers; the EEPROM is an external ROM, which saves the system settings and preset frequency data; The reference frequency is pre-divided to form the reference frequency for frequency discrimination and phase discrimination; the frequency discrimination-phase discrimination module completes the frequency discrimination and phase discrimination functions of the loop; the programmable frequency division module and the dual-mode pre-frequency division module together form a loop A frequency divider that can change the frequency division ratio in series; Pdhout and Pdlout are the error signals output by frequency and phase detection. The error signal is then passed through the loop filter to generate an error voltage to control the VCO, and the output of the VCO is fed back to the system. After the process of frequency division and phase locking, until the loop reaches the locked state, the output of the VCO is the required stable frequency.

3 Reference crossover module

The reference frequency division module mainly completes the pre-frequency division of the reference frequency (usually input by an external crystal oscillator), so as to output the reference frequency of frequency and phase detection.

In order to expand the range of the reference frequency, a 4-bit reference frequency division register (RCR) is used in the module, and the frequency division ratio of the reference frequency can be freely selected between 2 and 15. The implementation process is to use a 4-bit adding counter to count the reference frequency. The preset value of the counter is the reference frequency division value set in the RCR. After frequency division, the frequency output by the module is sent to the frequency discrimination-phase discrimination module. is used as the reference frequency for frequency discrimination and phase discrimination.

Figure 2 is the simulation waveform of the reference frequency division module. In the figure, reset is the reset signal, and the low level is valid; ref_f is the reference frequency of the input module; benchmark_f is the reference frequency output by the module after frequency division; the preset value in the RCR is HA, that is, the frequency division by 10.

4 Dual-mode prescaler module

The dual-mode pre-frequency division module mainly completes the pre-frequency division of the frequency fed back to the system by the VCO output, and the pre-frequency divided frequency is input to the programmable frequency divider for further frequency division.

In order to expand the output frequency range of the frequency synthesizer, in a frequency synthesis system with a relatively simple structure, the frequency of the VCO output fed back to the system is passed through a single-mode prescaler, and then sent to the programmable frequency divider after frequency division. Frequency division, although the structure is relatively simple, but it reduces the performance of the frequency synthesizer. If the output frequency of the frequency synthesizer is required to be increased, the pre-divider ratio should be increased, thereby reducing the resolution of the output frequency. In order to maintain a stable output frequency resolution and at the same time increase the output frequency of the frequency synthesizer, the system adopts a dual-mode prescaler. The dual-mode prescaler has two frequency division modes, corresponding to two frequency division ratios, and the modes are controlled by the dual-mode control logic (DMC). When DMC is 1, the prescaler works in the M frequency division mode, where M is the prescaler value preset in the 4-bit prescaler register (PSR). When DMC is 0, the prescaler works in the M+1 frequency division mode. The range of M is 2~15. The realization of its frequency division function also adopts the way of 4-bit adding counter.

Figure 3 is the simulation waveform of the dual-mode prescaler module. In the figure reset is the reset signal; dmc is the dual-mode control logic; vco_f is the frequency of the VCO output fed back to the system; prescaler_f is the output frequency after dual-mode pre-frequency division; the preset value in the PSR is H8, that is, 8/ 9 dual-modulus divider.

5 Programmable frequency division module

The programmable frequency division module mainly completes the frequency division of the frequency output by the pre-frequency division module, and completes the required frequency division function through the control of the DMC and the cooperation of the dual-mode pre-frequency division module.

The programmable frequency divider module consists of two programmable frequency dividers and a dual-mode control logic DMC. The frequency division ratio of the two programmable frequency dividers is determined by the frequency division values ​​in the programmable frequency division register A (PAR) and the programmable frequency division register B (PBR). The working principle of DMC is: frequency divider A and frequency divider B are composed of two 4-bit addition counters A and B respectively. The preset values ​​are the frequency division values ​​in PAR and PBR respectively. After the addition count starts, When neither of the two counters reaches the preset value, the DMC outputs 0, and the dual-modulus prescaler module works in the M+1 frequency division mode; when the counter B counts to the preset value, the DMC outputs 0. Output 1. At this time, the dual-mode pre-frequency division module works in the M frequency division mode. At the same time, the counter B stops working, the counter A continues to work, and counts up to the preset value, and then the counters A and B start new counting at the same time. Work. Assuming PAR=A, PBR=B, when the counter B counts to the preset value, including the count of the pre-frequency division, the total count is (M+1)×B, after which the counter B stops working, and the counter A continues The remaining (A-B) counts are completed. This stage includes the pre-frequency division counting and a total of M × (A-B), so when the two counters complete the counting in sequence, including the pre-frequency division counting. The total count is:

N=(M+1)×B+ M×(A-B)=MA+B, that is, the loop is divided by N.

It can be seen from the above analysis that the value in PAR must be greater than the value in PBR, otherwise the module will not operate normally.

Figure 4 is the simulation waveform of the programmable frequency division module. In the figure, reset is the reset signal; prescaler_f is the output frequency after dual-modulus pre-frequency division; prog_f is the output frequency of the module after frequency division by two programmable frequency dividers; the preset value of PAR is HC, that is, A= 12 frequency division; the preset value of PBR is H4, that is, B=4 frequency division; dmc is dual-mode control logic.

6 Frequency discrimination-phase discrimination module

The frequency discrimination-phase discrimination module mainly completes the frequency discrimination-phase discrimination on the frequency and the reference frequency of the input module after frequency division, and outputs the error result.

This module adopts lead and lag dual output mode: if the input frequency is higher than the reference frequency or the phase is leading, Pdhout outputs a negative pulse, while Pdlout outputs a high level; if the input frequency is lower than the reference frequency or phase lag, Pdhout outputs a high level When the input frequency and the reference frequency are in phase, both Pdlout and Pdhout output high level.

The working principle of the frequency discrimination-phase detection module is: when the input frequency and the reference frequency are different in frequency, the module works in the frequency discrimination mode; when the input frequency and the reference frequency are at the same frequency but different phases, the module works in the phase detection mode, thereby expanding the The fast capture band of the loop enables the loop to lock the phase relatively quickly, thereby achieving a closed-loop locked state. The digital frequency discrimination-phase discrimination module adopts a bottom-up design method, and its output mode and function conform to the state transition diagram shown in Figure 5.

In the figure, Negedge Benchm_f is the falling edge of the reference frequency waveform; Negedge Prog_f is the falling edge of the input frequency waveform; in the S0 state, the module outputs Pdhout=1, Pdlout=1, and it is in the same frequency and phase; in the S1 state, the module outputs Pdhout=0 , Pdlout=1, at this time the input frequency is higher than the reference frequency or the input frequency is ahead of the reference frequency phase; in S2 state, the module output Pdhout=1, Pdlout=0, at this time the input frequency is lower than the reference frequency or the input frequency is higher than the reference frequency phase lag.

Figures 6, 7, 8, and 9 are simulation diagrams at different input frequencies.

In the figure reset is the reset signal; benchmark_f is the reference frequency; prog_f is the input frequency; pdhout and pdlout are the outputs of the frequency discrimination-phase discrimination module.

7 CPU module

The CPU module mainly completes the control of the entire system. The CPU includes an 8-bit read data register (RDR); a 10-bit external EEPROM address register (EAR) with an addressing space of 1024 × 8 bits, supporting frequency synthesis of 1023 frequency points; four 4-bit frequency division registers , including the reference divider register (RCR), the prescaler register (PSR), the programmable divider register A (PAR) and the programmable divider register B (PBR).

The control in the CPU includes: read external program memory (EEPROM) control, program execution control, programmable frequency divider setting control, etc. The working process is as follows: the program counter of the CPU adopts the sequential increment counting method, and executes sequentially from the 000H address. The instructions in the external ROM are also stored sequentially from the 000H address, and the instructions do not need to be decoded. Corresponding method: address 000H, execute RCR=(000H)h, PSR=(000H)l; address 001H to 400H, store the preset frequency value table, execute PAR=(abcH)h, PBR=(abcH)l , where (xxxH)h and (xxxH)l represent the upper 4 bits and the lower 4 bits of the data stored in xxxH, respectively, and abcH represents an address from 001H to 3FFH currently executed. After the program sequence is executed to 3FFH, it will automatically return to the address 001H for cyclic execution. If there are no 1023 frequency points, all the addresses after the last frequency point can be stored in FFH. When the program runs to the address whose content is FFH, it will not perform any operation and immediately return to the 001H address to continue cyclic execution.

The read external program memory control section uses a 10-bit adding counter to form a sequentially increasing 10-bit address. At the same time, there should be a read enable read, and the program running control signal should be processed immediately, that is, the lock signal stop. When the stop signal is valid (low level), the output of the frequency synthesizer is locked at the current frequency point. The module also includes 10 address buses and 8 data buses. The program execution control part assigns a value to the corresponding register through the current address to generate different frequency division values.

During the simulation, Verilog HDL is used to write an external ROM simulation module with pre-stored data to simulate the CPU. The program is as follows:

module rom(_read,address,data);

input _read;

input [9:0] address;

output [7:0] data;

reg [7:0] data;

always @ (_read or address)

if(_read)

data《=8‘bzzzzzzzz;

else

case(address)

10’h000:data《=8‘ha8;

10’h001:data《=8‘h91;

…………………

10’h3fe:data《=8‘h87;

10’h3ff:data《=8‘h65;

endcase

endmodule

Figures 10 and 11 are the simulation waveforms. In the figure reset is the reset signal; stop is the lock signal; clk is the external clock of the CPU; clk1 is the 2-frequency signal of clk to provide the clock for the CPU to read data and generate addresses; read is also the 2-frequency signal of clk (phase and clk1 differs by π/2), provides read enable for external ROM, and provides the clock controlled by registers for CPU at the same time; address is the external ROM address bus; rom.data[7..0] is the data sent by the external ROM.

Responsible editor: gt

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