Digital down-conversion DDC (digital down lonvwrsionl) is used as a bridge between the front-end A/D converter of the system and the back-end general-purpose DSP device. By reducing the rate of data flow, the low-speed data is sent to the back-end general-purpose DSP device for processing. It will have a direct impact on the stability of the entire software radio system. The use of special DDC devices to complete digital down-conversion has the advantages of large extraction ratio and stable performance, but it is expensive and not flexible enough to fully reflect the advantages of software radio. Compared with ASIC and DSP, FPGA technology has developed rapidly and its processing capability has been greatly enhanced. Compared with ASIC and DSP, it has many advantages such as high throughput, short development cycle, and online reconfiguration. Based on these advantages, FPGA plays an important role in the research and development of software radio.
2 Digital down-conversion system
The functional structure of the digital downconverter in the software radio system is shown in Figure 1, which includes the direct digital frequency synthesizer DDS (direct digital synthesizer), digital mixer, FIR filter, decimation and other modules. The original analog IF signal is band-pass sampled by the A/D converter to obtain a digital IF signal. After being input to the DDC, it is first multiplied (digital mixing) with the two quadrature local oscillator signals generated by the DDS, and the digital IF is moved to the baseband. The data rate obtained after mixing is consistent with the sampling rate, and the post-stage FIR filter must reach this processing rate. The hardware implementation is rather difficult, so first the data rate is greatly reduced by a decimation block, and then the entire channel is shaped and filtered using a high-order FIR low-pass filter. The two channels of positive baseband signals output by filtering are handed over to the next-level DSP device for processing.
2.1 FPGA implementation of the mixer
The digital mixer multiplies the original sampled signal with the sine and cosine waveforms generated by the look-up table, and finally obtains two mutually orthogonal signals. Due to the high sampling rate of the input signal, the processing speed of the mixer is required to be greater than or equal to the signal sampling rate. A single-channel digital down-conversion system requires two digital mixers. That is, the multiplier. XC2V1000 device embeds 64 18 × 18-bit hardware multipliers, and its maximum operating frequency is 500 MHz, so the use of hardware multipliers can fully meet the design requirements of the mixer. The hardware multiplier configuration can be easily implemented using the MulTIplier IP core from Xilinx. Two 14-bit input signals are used in this design, and the output signal is also 14-bit. Figure 2 is a structural diagram of a mixer.
2.2 FPGA implementation of DDS
Using IPCORE in ISE to implement DDS, since the original signal is a 60±7 MHz bandpass signal, a 100 MHz MD converter generates a signal with an intermediate frequency of 40 MHz, and the DDS output frequency is set to 40 MHz, and the generated frequency is 40 MHz. The quadrature I/Q signal of No. 1 and the original signal are mixed to generate two zero-IF quadrature signals to realize down-conversion. The dynamic range (SFDR) of the DDS parameter setting is 80 dB; the frequency resolution (Frequency ResoluTIon) is 0.4Hz; the DDS output frequency (Frequency) is 40 MHz. The simulation result of DDS is shown in Fig. 3.
2.3 FPGA implementation of the extraction module
After mixing, two quadrature signals with a rate of 100 MHz and a bit width of 14 bits arrive at the decimation module. In order to process the two quadrature signals more conveniently, the signal rate needs to be reduced. In this design, the signal is extracted according to the ratio of 4:1. After the extraction is completed, it becomes a signal with a rate of 25 MHz and a bit width of 14 bits.
The realization of the extraction module is written in VHDL language in ISE. First divide the clock by 4, and divide the system clock 100 MHz into 25 MHz. Then use the 25 MHz clock to control two D flip-flops. Taking the two-way I and Q quadrature signals with a rate of 100 MHz and a bit width of 14 bits after mixing as the input signals of the two D flip-flops, the 4:1 extraction can be completed. After the decimation module, the signal becomes a signal with a rate of 25 MHz and a bit width of 14 bits. Fig. 4 is the simulation waveform of frequency division.
2.4 FPGA implementation of FIR filter
The FIR filter is also implemented by ISEIPCORE, because the signal after DDS is a zero-IF signal with a bandwidth of 14 MHz, and only the positive frequency range is considered, so the passband cutoff frequency of PFIR is 7 MHz, and a passband cutoff frequency is designed in MATLAB. For the FIR of 7 MHz, quantize the coefficients into 14-bit binary values and store them in the coefficient file*. coe, just import it into FIR; the higher the order of FIR (coefficient length), the better the performance, but considering the resource occupancy, the order of FIR should not be too high, and the design uses 35-order FIR. Therefore, the FIR parameters are set as: the result resolution (Result ResoluTIon) is 16 bits; the filter order (Fiher Length) is 35; the coefficient precision (Precision) is 14 bits. Figure 5 shows the structure of the FIR filter.
2.5 FPGA device selection
The design will perform digital down-conversion processing on high-speed band-pass signals with a sampling rate of 100 MHz, which requires high processing speed of the system. Because Xilinx's FPGA processing speed is faster than Ahera's, and it is better than Altera in system stability and operability. Considering that the digital down-conversion has higher requirements on the processing speed, reliability and stability of the system. Therefore, the XC2V1000 device of the Virtex-2 series of Xilinx Company is selected. The XCl2V1000 device contains 1 280 CLBs, each CLB is composed of 4 slices, a total of 5 120 slices, to meet the design requirements.
3 System debugging and result analysis
The development tool of Xilinx's FPGA is ISE, and the current version has been updated to lO. 2. ISE is an integrated development environment, including HDL editor, IP-CORE Cenerator System, constraint editor, static timing analysis tools, power analysis tools and more than ten tools. These tools can help designers improve their productivity. ISE can easily integrate third-party tools, such as the simulation tool Mod-elsim and the synthesis tool Synplify. In addition, the Xmnx tool Clfipseope can observe the FPGA internal signal waveform online, and the Plan Ahead tool can greatly reduce the design time by simplifying the steps between synthesis and placement and routing, and can achieve a 30% performance improvement when combined with ISE. Each module of DDC is realized by VHDL language under ISE environment. After hardware debugging, the system function is normal, import each part of the data generated by FPGA into MARLAB, and the obtained operation result waveform is shown in Figure 6.
The DDC module originally did not change the bit width of the input signal. The input was a 14-bit, 100 MHz single-channel signal, and the output should have been two channels of 14-bit bit-width, zero-IF quadrature signals at a rate of 100 MHz. The actual output is a zero-IF quadrature signal with a bit width of two channels of 30 bits and a rate of 100 MHz, so the two channels of 30-bit signals should be intercepted first, restored to a width of 14 bits, and then extracted. Experiments have verified that in the design, truncation of 13 to 26 bits for two channels (1/Q channel) of 30-bit signals has the best effect, and the signal quality performance can be guaranteed.
Using FPGA to realize DDC has the advantages of high speed and strong flexibility. The system design adopts Xilinx's FPGA platform, among which there are many free IP cores for selection, which can effectively reduce the development cycle and difficulty while achieving better performance. Therefore, the design scheme has wide application potential.
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