In the mid-1980s, the appearance of high-density programmable logic device (PLD) opened up a new way to realize digital logic circuit. High Density PLD can be divided into two categories: complex programmable logic device (CPLD) and field programmable gate array (FPGA). They are mainly based on three programming technologies: EEPROM (electrically erasable read only memory) with limited programming times (generally hundreds to tens of thousands of times), FPGA (programmable gate array) and FPGA (programmable gate array) SRAM (static random access memory) with unlimited programming times and antifuse (antifuse) with only one programming time. At present, the mainstream CPLD adopts the product term (P-term) structure based on EEPROM, while the mainstream FPGA adopts the look-up table (LUT) structure based on SRAM and the multiplexer structure based on antifuse. Among them, FPGA based on SRAM can be reconstructed in the system or even dynamically, so its application flexibility is the biggest.
The reconfigurable technology in recent ten years originated from the idea of FPGA programmable structure. This technology can get a good tradeoff between speed and flexibility in the application, and fill the gap between the traditional software and hardware application. Reconfigurable technology refers to the realization technology of using circuit construction system with hardware reconfigurable structure to meet a wide range of applications. Using FPGA as the core of reconfiguration system can not only greatly shorten the system development time, but also obtain high flexibility to save resources. FPGA contains a large number of flip flops (up to thousands) and LUTS with flexible structure, which is suitable for fine-grained and pipeline based general computing. For the application of reconfigurable multi bus control and different protocol processing related to data packets in network, the decoding and control of time-varying are needed. When the reconfiguration system completes the above application, it needs complex state machine and decoding circuit which can be dynamically reconstructed. Because the combinational logic in these circuits is complex and the number of inputs is large, but the number of flip flops is small, so the implementation of FPGA will cause a lot of waste of flip flops in the unit, and the performance will be greatly reduced by using the cascade connection of multiple LUTS to realize the combinational logic with large input, which is difficult to meet the speed requirements.
The structure of CPLD is very suitable for realizing the above logic functions. However, the EEPROM of CPLD has low programming speed and limited programming times, and is not suitable for the application of dynamic reconfiguration system which requires fast and frequent reconfiguration.
Obviously, the design of CPLD based on SRAM programming technology can solve the above problems. The key problem in the design and implementation of CPLD is the realization of the core programmable circuit structure. Therefore, this paper mainly discusses how to design a circuit structure with similar functions and based on SRAM programming technology according to the core programmable structure of CPLD, so as to better meet the application of complex state machine and decoding circuit in dynamic reconfiguration system.
Introduction of the core programmable structure of CPLD
CPLD consists of several macro units and programmable interconnects. Each macro cell consists of five product terms, one XOR gate, one 5-input or gate and one trigger. Product term is the core programmable structure of macro unit, which can flexibly realize the function of wide and gate with large number of inputs. As shown in Figure 1a, P-term is an array of EEPROM transistors. Each EEPROM transistor in the array is equivalent to a programmable switch. After programming, the eep2rom transistor in the “on” state acts as the pull-down switch of the wide and gate, just like the ordinary transistor, which is controlled by the gate input. The eep2rom transistor in the “off” state is open circuit, and the gate input has no contribution to the wide and gate. In this way, the logic function of P-term can be given by equation (1)
(a) Programmable wide and gate structure based on EEPROM
(b) Programmable structure of PIA in MAX7000
Figure 1 circuit structure diagram
In equation (1), C1 ~ CN correspond to the state of N EEPROM transistors in Figure 1 (a) after programming. When the EEPROM transistor at the I (I = 1-N) th position is on, CI is 0, otherwise, CI is 1. At present, mainstream CPLDs all adopt this structure, such as Altera’s MAX7000 series and max9000 series, Xilinx’s xc9500 series and lattice’s ispLSI series.
Programmable interconnect is another core programmable structure in CPLD. The structure is an interconnection network with a large number of programmable switches, which provides flexible interconnection between the I / O pins of the chip and the input and output of the macro unit. Fixed delay is the most prominent feature of programmable interconnect in CPLD. Different from FPGA’s segmented programmable interconnection mode, CPLD adopts global programmable interconnection network to allocate interconnection resources centrally, so that the delay from the beginning to the end of the connection path is fixed. In FPGA, the number of segmented lines from the beginning to the end of the connection path is not fixed, so the delay is not fixed. In contrast, CPLD can eliminate the skew between signals when it realizes complex combinational logic, and it is easier to eliminate the phenomenon of competition and risk. At present, the mainstream CPLD adopts continuous interconnect structure, such as PIA structure in MAX7000 and fastconnect structure in xc9500. Figure 1 (b) shows the logical structure of PIA in MAX7000. In this architecture, EEPROM transistors of each programming node control one input of 2-input and gate to decide the signal of the other input.
To sum up, the core programmable structure of CPLD is P-term and programmable interconnect structure with fixed delay.
Design of PLD circuit structure based on SRAM programming technology
Aiming at the core programmable structure of CPLD – P-term and programmable interconnect with fixed delay, a new circuit structure based on SRAM programming technology is designed, which is introduced in detail below.
Circuit structure design of SRAM programming unit
The programming technology based on SRAM is to store every bit configuration data of PLD in SRAM cell. As shown in Figure 2a,
(a) SRAM programming cell structure
(b) HSPICE simulation results of SRAM cell
Figure 2 circuit structure and simulation results
This design adopts 5-tube SRAM structure. The structure consists of two CMOS reversers to form a bistable loop. Unlike ordinary SRAM, the SRAM programming unit of PLD does not need to read function, only need to write word line and bit line. The output signals Q and QN in Fig. 2 (a) directly control the transistor on or off to complete the programmable function. The key of this structure design is to select the appropriate transistor size to ensure that the normal logic value of the data signal can change the state of the cell when the word line is gated to the bit line. Therefore, the design determines that the transistor controlled by word line and reverser a have strong driving ability, while the reverser B has weak driving ability. The width to length ratio of transistor is adjusted appropriately to ensure the fast writing of programming data. Figure 2 (b) shows the HSPICE simulation results of the SRAM cell (based on 2.5V, 0.25V) μ The following simulation results are based on the model parameters of the mcmos process library. The two curves a and B in the figure represent the signal Q and QN respectively. (1) and (2) in Fig. 2 (b) show the changes of Q and QN when writing high level (low level is stored in the cell) and low level (high level is stored in the cell), respectively. As can be seen from the figure, the maximum write delay is about 650ps, which occurs when the write level is high. In this way, the structure can fully meet the configuration speed requirements of high-speed reconfiguration.
Design of P-term circuit structure based on SRAM programming technology
The design core of P-term structure based on SRAM is the structure design of programmable wide and gate, which can realize the function of formula (1). Theoretically, there are many structures to realize the function of formula (1), such as the logic composed of static CMOS logic gates or transmission gates. However, the number of P-term inputs is huge, up to 88 inputs. Therefore, the above structure is not acceptable in terms of circuit area and performance. The NMOS like circuit structure can achieve good results in area and performance, but this circuit has a DC path from power supply to ground at low output level, which leads to static power consumption, and the output low level is not 0, which is determined by the partial voltage ratio of pull-up and pull-down turn-on resistors. It can be seen that the key point of this circuit design is the design of pull-up structure. The SRAM based programmable wide and gate architecture designed in this paper is based on the NMOS like architecture. The programmable pull-up architecture is used to control the tradeoff between power consumption and performance.
The circuit structure designed in this paper is shown in Figure 3 (a), the number of inputs n = 88. NMOS transistors are used to form a pull-down network, and the pull-down structure corresponding to each input is NMOS transistors controlled by input and NMOS transistors controlled by SRAM in series. The programming data in SRAM controls the switch of corresponding transistor to decide the corresponding and gate input. The output adopts two reversers to form a buffer to solve the problem that the output low level of NMOS like circuit is not 0. The programmable pull-up structure consists of three PMOS transistors a, B and C in parallel. The PMOS transistors C are normally on, and a and B are controlled on or off by SRAM programming. In this way, under the programming control of srama and sramb, the architecture has three different speed and power consumption modes: high speed and high power consumption (PMOS A and B are all on), medium speed and medium power consumption (a is on but B is not on) and low speed and low power consumption (a and B are not on). Since the on resistance of the three PMOS transistors is much larger than that of the pull-down NMOS transistors, the key path of this structure is the high-level charging path indicated by the dotted line in the figure.
Under the above three working modes, the HSPICE simulation results of critical path are shown in Fig. 3 (b), in which (1), (2) and (3) respectively show the change of output pout from low level to high level caused by the change of input signal from high level to low level under the three modes, and curve A is the input signal, and curve B is the output signal pout. In the high-speed mode, the critical path delay is about 1.2 ns, but the quiescent current from the power supply to the ground is 56 μ A； In the medium speed mode, the critical path delay is about 2.2 ns, and the quiescent current is 29 μ A； In the low power mode, the critical path delay is about 4ns and the quiescent current is only 14 μ A。
(a) Programmable wide and gate structure based on SRAM
(b) HSPICE simulation results of wide and gate critical path
Figure 3 circuit structure and simulation results
Design of programmable interconnect circuit structure based on SRAM programming technology
The function of programmable interconnects in CPLD is to distribute input signals to the input of macro unit (the input of P-term) with fixed delay. The programmable interconnect designed in this paper is a two-dimensional array composed of programmable interconnect units with the same structure. The input signal of each unit comes directly from the input bus, and the output signal goes directly to the macro unit, so that the delay can be fixed. Therefore, the design of this structure is essentially the structure design of programmable connection unit.
The structure of the programmable connection unit based on SRAM designed in this paper is shown in Figure 4 (a). The function of this structure is to select one or none of the eight input lines and only select the low-level output, then turn the selected output into positive and negative signals and output them to the input of P-term in the macrocell. The core structure is the multiplexer controlled by SRAM, in which the SRAM programming control bits sram1-sram3
(a) Circuit structure of programmable interconnect unit based on SRAM
(b) HSPICE simulation results of critical path of programmable interconnect unit
Figure 4 circuit structure and simulation results
Control multiplexer to achieve one out of eight connection state, and sram4 control switch to achieve low output level. In this design, only a single NMOS transistor is used to form a multiplexer. Compared with the case of using the transmission gate, each switch reduces one transistor. However, there is threshold loss in the high level of NMOS transmission. Therefore, when selecting the appropriate transistor size, reversers A and B are added at the third and fourth level switches to ensure the output high level amplitude and sufficient driving ability. Programmable interconnect delay plays a decisive role in PLD speed. The dashed line in Figure 4 (a) is the critical path of the structure, and the HSPICE simulation results of the critical path are shown in Figure 4 (b). (1) and (2) are the changes of the output caused by the rise and fall of the input signal, respectively. The three curves a, B and C represent the input bus signal, the positive and negative output signals out and OUTN, respectively. The simulation results show that the maximum delay of this structure is only 300ps.
In particular, this structure only uses 4 bit SRAM programming to realize the function of a group of switches in the pia unit of MAX7000, while the structure in Figure 1 (b) needs 8 bit EEPROM. In this way, compared with the structure based on EEPROM, this structure reduces the programming data by 4 bits, so that the programming data of the programmable interconnect based on this structure is reduced by 50%. The reduction of programming data can shorten the time of device configuration and improve the efficiency of dynamic reconfiguration in the application of reconfiguration system.
Aiming at the core programmable structure of traditional CPLD – P-term and programmable interconnect, this paper adopts 2.5V, 0.25V μ A new reconfigurable circuit structure based on SRAM is designed in mcmos technology. The P-term structure in this design has three programmable working modes, which can achieve a better tradeoff between speed and power consumption. SRAM based programmable interconnect with fixed delay only has 300ps delay time, which can achieve high speed. Compared with EEPROM based interconnect, the programming data is reduced by 50%, which can obtain shorter configuration time and is more suitable for dynamic reconfiguration applications. Compared with FPGA, PLD based on the new structure is more suitable for implementing complex state machine and decoding circuit in reconfigurable system.
Editor in charge: GT