In this paper, a CMOS power amplifier for headphone driver is designed. The amplifier adopts 0.35 μ M double-layer polysilicon process, driving 32 Ω resistive load. The design adopts the circuit structure of three-stage amplification and two-stage Miller compensation, and improves the performance of the audio amplifier by increasing the gain bandwidth. The simulation results show that the open-loop DC gain of the circuit is 70dB, the phase margin is 86.6 °, and the unit gain bandwidth is 100MHz. The output stage adopts push-pull class AB structure, which can effectively improve the swing of output voltage, so as to obtain the high driving ability of the circuit under low power supply voltage. The results show that the voltage output swing is 2.7V at 3.3V supply voltage.

Low power consumption and high performance is the goal of audio amplifier. In recent years, CMOS power amplifier has been greatly developed. Using this process will effectively reduce power consumption, but the following problems are how to obtain effective gain bandwidth, reduce the noise generated by power supply, how to effectively reduce harmonic distortion, and obtain almost full output at low power supply voltage to obtain effective voltage output.

The amplifier with two-stage Miller compensation structure introduced in this paper has simple structure and meets the requirements of gain bandwidth and voltage output swing.

Structure of amplifier

The power amplifier adopts three-stage amplification structure. The input stage is a folding amplification structure, and the input tube is a p tube to reduce flicker noise. The output of the folding input stage is directly used as the drive of the p-channel transistor in the output stage.

The second stage is a non inverting amplifier stage, which consists of a common source p-channel input tube, a current mirror and a current of 80 μ A is composed of constant current source. The important function of this stage circuit is to provide a reasonable bias voltage for the n-tube of the output stage, so as to separate the bias voltage of the two tubes of the output stage, so as to realize class AB output.

The output stage is a push-pull type AB structure, which is characterized by the alternating conduction of P tube and N tube, so that the output voltage only loses the overdrive voltage of one tube, effectively improves the level of output voltage and meets the requirements of signal output drive under low power supply voltage. The static current of the output stage of the circuit is 1mA. There are two Miller type compensation circuits between the output stage of the amplifier and the first and second stages. The miller compensation adopts the zero resistance compensation method. This method eliminates the right half plane (RHP) zero effect caused only by capacitance compensation by connecting the compensation capacitor CC in series with a resistor RZ, and increases the stability of the circuit.

Npower2 line is used for power saving control. When its value is low potential, the whole circuit does not work and is in the power saving state. Power saving control is very necessary for portable systems.

The specific structure is shown in Figure 1, where VP1, VP2, vn2 and vn2 are bias voltages.

Design of CMOS power amplifier based on two-stage Miller compensation structure

Fig. 1 Structure of amplifier circuit

Stability analysis of amplifier circuit

Pole frequency of open-loop response without compensation capacitance and resistance

f1=1/(2πR1C1);  f2=1/(2πR2C2); f3=1/(2πR3C3),

Where: RI and CI (I = 1, 2, 3) are the equivalent input resistance and capacitance of stage I respectively, where R3 is the output load resistance.

The stability design condition of the three-stage power amplifier with compensation is that the main pole F1 ≤ FTN, n = 2,3,, N, FT is the unit gain frequency of the amplifier, that is, the open-loop gain decreases at a rate of 20dB per 10 octave in the frequency range of ft.

Fig. 2 is the simulation result of the baud phase characteristics of the uncompensated three-stage amplifier with 32 Ω load. From this figure, it can be seen that there are two poles in the unit gain frequency range before compensation, the phase margin is only 36 °, and the circuit is not stable enough.

Fig. 2 baud phase diagram without compensation

Fig. 3 shows the simulation results of a three-stage amplifier with a load of 32 Ω after compensation. The poles of F1 and F2 are effectively separated by compensation. F1 moves to the low-frequency point and moves to a lower frequency, while F2 moves outside the FT frequency to a very high frequency. From F1 ≤ ft2, the pole satisfies the stability condition of the circuit.

Fig. 3 baud phase diagram after compensation

Using two-stage zero resistance compensation method, two zeros will be introduced, one is the right half plane (RHP) zero and the other is the left half plane (LHP) zero. Their values are: zrhp = 1 / (CC2 / gm3-rz2cc2); Zlhp = – 1 / (rz1cc1), where CC1, RZ1, CC2 and rz2 are the compensation capacitance and resistance of the first stage and the second stage respectively, and GM3 is the transconductance of the third stage.

The existence of zero point in the right half plane will slow down the decrease of amplitude, so the gain intersection is extrapolated and farther away from the origin, which greatly reduces the stability of the circuit, so it must be eliminated. From the formula of the zero point of the right half plane, it can be deduced theoretically that if the value of the zero resistance rz2 is selected so that rz2 = 1 / GM3, the zero point of the right half plane will be moved to infinity, which will no longer affect the stability of the circuit. However, in the actual working circuit, the transconductance compensation resistance of the output tube will deviate from the theoretical value due to the changes of working current, temperature, process and other factors, so the equal requirements of the two can not be met. In the actual design, there is no such strict requirement. Generally, as long as the position of the zero point meets more than 10 times the unit gain frequency, the influence of the zero point on the circuit stability can be ignored.

As can be seen from Fig. 3, the phase margin of the circuit can reach 86.6 ° in the open-loop case. At this time, the gain bandwidth is 100MHz, and the stability of the circuit is greatly improved.

The following will discuss how the left half plane zero and the right half plane zero meet the requirements in this design.

As can be seen from the previous analysis and figure 3, the reason why the bandwidth of the whole circuit is up to 100MHz is mainly that the value of the zero point in the left half plane is low, which slows down the decline of amplitude and phase in the unit gain band. Although this zero point is harmless in the designed circuit, according to the requirements of headphone audio circuit, 100MHz bandwidth is completely unnecessary, so it can be slightly improved on the basis of this circuit. Change the resistance RZ1 to 100 Ω, and the size of compensation capacitor CC1 remains unchanged. Then the value of zero point in the left half plane is 350MHz, and the unit gain frequency is 32mhz, The zero point of the left half plane has no effect on the unit gain bandwidth.

For the zero point of the right half plane, if the compensation capacitance CC2 is 2pF and the compensation resistance rz2 is 1K Ω, it can be deduced that (1 / gm3-rz2) has a large variation range from the zero point formula of the right half plane and the conditions it should meet (zrhp ≥ 10 times the gain bandwidth). In other words, transconductance and resistance can vary with the actual working current, temperature, process and other conditions, and a large variation range is allowed.

The output load of the circuit is a resistance of 32 Ω. Because this design uses a single power supply and the output bias is 1.65v, a large output coupling capacitor needs to be connected in series in the actual circuit to prevent the power loss caused by DC current flowing through the headset, which may even damage the headset or headset drive. 220 is used in this circuit μ F capacitance. The addition of this capacitor has a certain impact on the low-frequency response of the circuit, but it still meets the requirements of human hearing range.

Swing of output voltage

For portable power amplifier, due to the reduction of its power supply voltage, in order to obtain effective output voltage, the output swing is required to be as close to the full range as possible. The design circuit adopts class AB output structure, so the output voltage only loses an n-tube or p-tube overdrive voltage, which greatly improves the range of output voltage. Next, based on the AB output stage, we will study how to reduce the overdrive voltage of n-tube and p-tube to further improve the voltage swing. Taking n tube as an example, the static current flowing through n tube when it is saturated and turned on is 1mA. Under this current, if the aspect ratio of output tube is large, the overdrive voltage vdsat = vgs-vtn can have a small value, so that the minimum value of output voltage will be reduced and the output range will be increased. Similar to the p-tube, a large aspect ratio can also improve the output level of the maximum voltage. The aspect ratio of p-tube is 3072 / 1 and that of n-tube is 768 / 1. Of course, the larger aspect ratio is obtained at the expense of area, but the aspect ratio of the output stage of this circuit is much smaller than that of similar circuits.

The maximum output swing of the circuit can reach 2.7V and the output voltage efficiency is 81.8%. It belongs to large output voltage swing. At this time, the corresponding maximum output power is 29MW.

Amplifier distortion

An important performance index of power amplifier is total harmonic distortion plus noise. Total harmonic distortion is mainly caused by nonlinear components. Even harmonic distortion can be eliminated when the circuit structure is completely symmetrical and there is no component mismatch, but in fact, such a rigorous circuit does not exist, and for audio circuits, odd harmonic distortion has a great impact on sound quality. Because the human ear is more sensitive to odd harmonic distortion, while the dual harmonic is much worse. The method of reducing total harmonic is generally to add an appropriate amount of internal feedback loop and select devices with good linearity. The three-stage amplifier circuit used in this paper has two internal feedback loops, which effectively suppresses harmonic distortion compared with the two-stage amplifier circuit.

It is measured that the total harmonic plus distortion of the three-stage amplifier circuit is – 68dB under 3.3V power supply voltage, 1kHz input signal frequency, 0dB gain and full swing, i.e. 2.7V output voltage.

Responsible editor: GT

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