introduction

Can (controller area network) is an advanced serial communication protocol, which was developed by Bosch Company of Germany and finally became the international standard (iso11898). It is one of the most widely used Fieldbus in the world. At present, there are more than 20 can bus controller manufacturers in the world, more than 110 can bus controller chips and microprocessor chips integrated with CAN bus controller.

Because the customized can bus controller chip can’t be embedded into SOC (system on chip), the use of discrete components to achieve can bus interface makes the number of devices in the system increase, and also increases the system area. The CAN bus controller introduced in this paper is made by Verilog HDL language description, can be used as an independent device, can also be integrated into FPGA as a module.

Although many people have studied or designed the IP core of CAN bus controller at home and abroad, most of them only research and design a certain module in the controller, and do not realize the function of a complete can bus controller. For example, the literature only studies the state machine of CAN controller, and only studies the bit timing module of CAN controller. However, the highest working frequency of CAN bus controller is not ideal, such as mcan2d1 CAN2.0 network provided by mentor graphics company The maximum working frequency of controller is only 32.46mhz, and the highest working frequency of CAN bus controller introduced in the literature is only 50MHz. Obviously, these IP cores can not adapt to the requirements of high-speed environment. Meanwhile, the external interface of the controller introduced in the literature has some interfaces such as register enabling bit. This interface does not conform to Avalon bus specification and is not conducive to integration into FPGA chip Therefore, it is still of great significance to research and design a high-speed and universal can bus controller IP core.

1. System implementation

1.1 system block diagram

In this design, the whole can controller system is divided into 11 modules, which are Avalon bus interface module, register group module, receive buffer module, transmit buffer module, receive filter module, CRC check module, state machine module, identifier filling module, error counter module, bit filling module and bit timing module. The structure diagram is shown in Fig. 1.

Design of CAN bus controller based on Verilog HDL language and Modelsim software

1.2 introduction of main modules

1.2.1 register group module

This module is implemented by a register group with bit width of 8bit and depth of 256. Among them, 23 registers have been used, and the rest are for future expansion. This design adopts the design idea of integrating the independent control and state registers. Any initialization of the controller and the receiving and sending of data are started from the write register group.

1.2.2 CRC verification module

CRC (cyclic redundancy check code) is a very powerful error detection and error correction code, which is often used in the data communication between auxiliary memory and host computer and computer network. Its basic principle is: after the k-bit information code, the R-bit check code is spliced, and the whole coding length is n bits. Therefore, this kind of code is also called (n, K) code. For a given (n, K) code, it can be proved that there exists a polynomial g (x) with the highest power n-k = R. according to G (x), a check code with seven bits information can be generated, and G (x) is called the generating polynomial of the CRC code.

Can bus protocol is CRC check, and it is a 16 bit CRC-16 check code. The generated polynomial isCan be converted to binary code group 1100010110011001. The specific process of generating CRC code is as follows: the divisor composed of frame start, arbitration field, control field and data field (data frame has data field, remote frame has no data field) is shifted to the right by 15 bits and divided by module 2 with binary code group generating polynomial. The generated 15 bit remainder is the required CRC code.

The main functions of this module are as follows: 1) when the controller is in the sending state, the CRC code is calculated, and the frame start, arbitration field, control field, (data field) and cro field are packed according to the requirements of frame format; 2) when the controller is in the receiving state, the number of dividers and generation composed of frame start, arbitration field, control field, (data field) and CRC field will be generated The binary code group of the term is divided by modulo 2. If the result is 0, the data will be accepted. If not, the data will be discarded and CRC error will be generated.

1.2.3 vertical filling module

In CAN bus protocol, when the controller is in the sending or receiving state, if the controller detects six consecutive levels of the same polarity on the bus (except for the end of the frame), the controller will detect an error and stop sending or receiving data. At this time, the controller will change from sending or receiving state to error state.

The main function of this module is: when sending 5 bits of the same polarity continuously, if the polarity of the 5th bit is different from that of the 6th bit to be transmitted, a bit with the same polarity as the 6th bit will be inserted between the 5th bit and 6th bit; if the 5th bit is the same as the 6th bit to be transmitted, a bit with opposite polarity to the 6th bit is inserted between the 5th bit and 6th bit; in the receiving state, if the polarity of the 5th bit is different from that of the 6th bit to be transmitted, If the polarity of bit 6 is different from that of the previous 5 bits, bit 6 will be discarded if the polarity of bit 6 is different from that of the previous 5 bits. If the polarity of bit 6 is the same as that of the previous 5 bits, a bit filling error will be generated, and the controller will stop receiving data. At this time, the controller will also change from receiving state to error state. At the same time, this module also has the function of detecting bit error, bit filling error, form error and reply error. In addition, the module also has the function of generating error frame, overload frame and intermittent frame.

1.2.4 state machine module

The state machine module plays the role of “brain” in the whole controller, which controls the operation of other modules. Compared with the design without state machine in the literature, using state opportunity makes the function of each module more clear, the system structure more clear and reasonable, and also more convenient for the coordinated control of each module. The controller is divided into 10 modes: bus off, bus start, bus idle, mode selection, send mode, receive mode, error mode, intermittent mode, overload mode and suspend mode. The state transition diagram of can state machine is shown in Figure 2.

Design of CAN bus controller based on Verilog HDL language and Modelsim software

Power down, reset and too many errors on the bus will cause the controller to enter the bus off mode; the next clock after system power on, reset release or too many errors will make the controller enter the bus start mode; in the bus start mode, if the controller enters the bus off mode due to power down or reset before, when the controller monitors 11 consecutive recessive bits on the bus once( When the logic level is 1 “), the controller enters the bus idle state. If the controller enters the bus off mode due to too many errors, the controller enters the bus idle mode when the controller detects 128 consecutive recessive bits on the bus; when the controller does not send data but detects that there are dominant bits on the bus (logic level” 0 “), the controller enters the receiving mode When the controller sends data and detects that there is a dominant bit on the bus, the controller enters the mode selection mode; mode selection is actually a bus arbitration, in which the identifier plays the role of arbitration bit, and the dominant bit has higher priority. If the bus arbitration fails, the controller enters the receiving mode, and if the arbitration is successful, it enters the transmission mode; after a frame of data is successfully sent, the controller enters the mode of mode selection, The controller will enter the intermittent mode; if the intermittent frame is sent successfully, the controller will enter the bus idle mode again. The simulation diagram of state machine from idle mode to mode selection mode is shown in Figure 3.

Design of CAN bus controller based on Verilog HDL language and Modelsim software

1.2.5 bit timing module

The bit timing module controls the rhythm of sending or receiving messages from the controller. This rhythm is called bit time, which is composed of four parts: synchronization section, propagation section, phase buffer section 1 and phase buffer section 2. These four segments are all composed of time shares. The time share is obtained by dividing the input clock according to the preset frequency division value.

Another important function of bit timing module is to synchronize the clock between the node and other nodes on the bus. Since each can node uses an independent clock, there will be phase differences between different nodes, which will affect the accuracy of message sending and receiving when the phase difference is serious. Therefore, it is necessary to synchronize the clock of different nodes.

2. System verification

The function simulation and time sequence simulation of the whole system are completed with Modelsim software. Figure 4 shows the verification of the data sent by the controller. The sending data for the test is randomly selected: 00101001, and the arbitration field and control field are optional, respectively: 110100101110 and 110001. After setting the register group, the controller calculates the corresponding CRC code as 110111001111 011, and then the controller packs and sends the data bit by bit according to the frame format of CAN protocol.

Design of CAN bus controller based on Verilog HDL language and Modelsim software

At first, the controller is in the bus off mode. After the reset, the controller enters the bus start mode. When the controller detects 11 consecutive recessive bits on the bus, it enters the bus idle mode. Then, when the controller detects the first dominant bit of the bus, it enters the mode selection mode. In this mode, the operation of the controller is bus arbitration to determine whether the node is in or not To obtain the bus control right, the test adopts the controller self-test mode, that is, the output line is connected with the input line, so the arbitration time is 12 bits. After the arbitration is successful, the controller will enter the sending mode. If there is no error, the controller will enter the intermittent mode after data transmission, and finally enter the bus idle mode.

After a series of tests and verification, it shows that the CAN bus controller can send or receive all the message frames conforming to can2.0a protocol.

3. Conclusion

This design realizes all can bus controller functions in accordance with can2.0a protocol, and the highest working frequency is 139.43mhz, which also achieves the original design purpose. The timing analysis of the controller is shown in Figure 5.

Design of CAN bus controller based on Verilog HDL language and Modelsim software

The innovation points of the author are as follows: firstly, the peripheral interface of the controller adopts Avalon bus interface, which makes the design more universal; secondly, the highest working frequency of the design reaches 139.43mhz, which can meet the requirements of high-speed communication.

Editor in charge: GT

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