1 Overview

In the design and implementation process of the communication system, it is necessary to test the bit error performance of the system. However, most of the common bit error rate testers are dedicated to testing various standard high-speed channels, which are inconvenient to test a large number of dedicated channels in practical applications, and are expensive and complicated to build a test platform. With the rapid development of large-scale integrated circuits, FPGA can achieve more and more complex design functions while maintaining its high integration, small size, low power consumption, and high cost performance, and is increasingly widely used in the design and implementation of communication equipment. .

This paper proposes a FPGA-based bit error rate tester solution, which uses a Cyclone series FPGA (EP1C6-144T) of Altera Corporation and related peripheral circuits to realize the bit error test function. The main control computer can be built through the FPGA. The asynchronous serial interface (UART) configures the error tester and reads the error information, and the computer completes the error analysis. At the same time, the program also provides a simple data display, which can perform qualitative analysis of the working performance of the communication system without the computer.

2. System composition and workflow

According to the completed functions, the whole system can be divided into six parts: test code generation unit, error code test unit, interface unit, display unit, clock generation unit, and control test software running on the main control computer. The specific block diagram is shown in Figure 1. .

Figure 1. Block diagram of the error tester 1 and 2, the workflow of the system is described as follows.

Figure 2 The block diagram of the error test of the communication system

According to the data rate of the communication system to be tested, the computer configures the clock generation unit through the UART, and obtains the parameters of the working clock and each enabled counter, so that the system works according to the predetermined clock; the test code generation unit sends the test code to the set clock according to the set clock. The transmission equipment of the system under test; after the transmission signal passes through the channel emulator, the receiving unit of the system under test receives and judges, and then sends the received data and the recovered data clock to the error code tester; the error code in the error code tester After the test unit completes the synchronization of the input data and the local data, it compares the input data with the local data, counts the number of errors, and sends the error information to the computer through the UART after completing the data comparison of two test cycles. At the same time, the number of error codes is transmitted to the display unit, and after processing, it drives four external seven-segment digital tubes to display the error rate in this test code cycle.

3. Key technologies and their realization

3.1 Generation of test code

This design uses m-sequence as the test code, and the m-sequence generator generates m-sequence for low-speed data transmission equipment testing error code according to the CCITT recommendation. Its characteristic polynomial is x9+x4+1 and the period is 512. Using the pseudo-random characteristics of the m-sequence, the communication performance of the system under different input combinations can be well tested. At the same time, the strong autocorrelation of the m-sequence is convenient for the tester to synchronize the input data with the local test code, so that the Error count.

3.2 Implementation of Error Test Unit

The bit error test unit is the core unit of the entire system, and its functional block diagram is shown in Figure 3. The function of the sequence synchronization tracking unit is to use the autocorrelation characteristic of the m sequence to synchronize the input data with the local m sequence, and transmit the synchronization information to the symbol comparison unit.

We use the autocorrelation of the test sequence-m-sequence to synchronize the received sequence with the local sequence. There are many ways to capture the m-sequence, usually the correlator method and the cyclic accumulation method are used. The advantage of the correlator method is that the acquisition speed is fast, usually the acquisition time does not exceed two cycles of the m-sequence, but the biggest problem of the correlator is that it requires too many logic resources. In contrast, the cyclic accumulation method requires very few logic resources. Although the capture delay is long, it is usually tolerable in the test environment. In addition, we can take certain measures to further reduce the capture delay. The working principle of the cyclic accumulator is as follows. After the system is reset, the m-sequence generator generates the m-sequence according to the preset parameters and stores it in the m-sequence buffer. After the symbols are synchronized, under the control of the address generator, the m-sequence is removed from the buffer. Read out in the area, perform the same-OR operation with the input sequence by bit, and then perform arithmetic addition. After the sum obtained by the addition is buffered by the D flip-flop for one clock cycle, it is input to the adder as an addend for the next addition operation, thereby realizing Cyclic accumulation of the local sequence with the input sequence. The accumulating and sending threshold detector is compared with the set threshold. If it is lower than the threshold, the address generation enable and synchronization indication output are invalid, and it is '0'. If it is higher than the set threshold, the two signals are set high. The following symbol comparison unit starts to work to compare the input sequence with the local sequence. The address generated by the address generator consists of two parts, namely:

Address output = accumulated address + offset address

The initial value of the two addresses is '0', the accumulated address count range is the same as the length of the m sequence, and 1 is added to each clock cycle. The m sequence output in the first cycle starts from the first symbol, and adds one. After the m sequence period, the address generator checks the address generation control signal input by the threshold detection. If the signal is '0', it means that the input sequence is not synchronized with the local sequence, and there is a phase difference. At this time, the offset address is incremented by 1. The accumulating address starts accumulating again, so that the m-sequence output in the second cycle starts to be output from the second symbol, which realizes the "sliding" of the local m-sequence relative to the input sequence.

After the sliding of the local code, it is completely synchronized with the input sequence. According to the correlation of the m sequence, the accumulated value will have a correlation peak and exceed the threshold value of the threshold detection. At this time, the threshold detection unit will set the address generation control signal to '1' ', the offset address of the address generator does not change, and the accumulated address continues to be counted cyclically. According to the input address, the m-sequence buffer outputs the m-sequence synchronized with the input sequence to the threshold detection unit and the symbol comparison unit. The UART sends a message to the host PC to start the bit error test.

After the sequence synchronization is completed, the threshold detection unit continues to work to check the synchronization status of the sequence. When the correlation peak value is lower than the threshold at a certain moment, it can be judged that the system bit error rate is too high, or the frame loss occurs during the data transmission process. At this time, the threshold detection unit disables the synchronization indication and address generation enable at the same time, starts a new round of capture, and at the same time sends an alarm to stop the error test to the main control PC through the UART, and waits for the start of the next statistics. It can be seen that the design index of the system bit error performance and the threshold in the threshold detection unit can establish a corresponding relationship, which is convenient for parameter setting before testing. Figure 4 is a timing simulation diagram of the test code capture. In order to test the error statistics function, we invert the first three codes of the test code to form a code error. As can be seen from the figure, when the sum of the accumulator is higher than the threshold, the synchronization indication is high, and when a new test code cycle starts, the error count starts, the first three test codes are wrong, and the error can be seen The code count correctly counts the number of errors.

The code element comparison unit performs the bitwise XOR operation on the received sequence through the locally generated m sequence, and outputs a count pulse every time an error occurs. According to the preset parameters, the error counting unit transmits the number of error codes through the UART after detecting two test code cycles, which is convenient for the main control computer to count the error code information.

The error code testing unit communicates with the PC through the UART, and sends the error information to the PC. The PC analyzes and processes the error data and forms a report. UART? The baud rate of 57.6Kbps is obtained by dividing the clock frequency of 10MHz provided by the system.

3.3 Real-time display of bit error rate

The real-time display of the bit error rate is realized by four seven-segment digital tubes with common cathodes. It is mainly used when the bit error tester is working away from the main control computer. Through the bit error statistics of every two test bit cycles, this is calculated. The real-time bit error rate of the time period is displayed on the seven-segment digital tube by scientific notation, so as to conduct a qualitative analysis of the operation of the communication system. The first nixie tube displays the one digit and the decimal point, the second nixie tube displays the first digit after the decimal point, the third one displays the minus sign, and the fourth one displays a single digit, which represents the negative number of scientific notation. In the following, 256 error codes are counted in two test code cycles (1024 codes) as an example to illustrate how to obtain the real-time display. First, send the number of bit errors into the comparator, and compare them with 11 and 102 respectively. 256 is greater than 102, indicating that the bit error rate is in the order of 101, and the fourth digital tube displays 1, and then 1/101×256=2560= ( 1010 0000 0000) The 12th and 11th digits of 2 are taken out, that is (10)2=2, as the single digit displayed by the first digital tube, and the 10th, 9th and 8th digits are taken out, That is, (100)2 is calculated as 0.5 as a binary decimal, then the second digital tube displays 5. When calculating the fractional part, the table look-up method can be used to directly obtain the output value to simplify the calculation.

3.4 Design of software testing platform

We use Visual C++++ and matlab mixed programming to realize the software testing platform. Visual C++ is a powerful software development and debugging tool launched by Microsoft. It is very convenient for the bottom operation of the computer. It is a very mature technology to program the serial port through API functions. Matlab is a scientific computing software released by Math Work. It has powerful drawing functions and a rich library of functions, providing powerful support for data analysis and chart production. The basic idea of ​​the software test platform is to use Visual C++ to compile the human-computer interaction interface of the platform, and to complete the data communication with the error test core, and then call the functions in matlab to analyze and output the obtained test data. The error event and its occurrence time are displayed on the interface.

4 Conclusion

This paper proposes a design and implementation scheme of a bit error rate tester based on FPGA, which is small in size, low in cost and flexible in use. With the advantage of strong processing ability, it has obtained better system performance and can be easily used in the development and testing of communication equipment.

At the same time, using the in-line programmable (ISP) capability of FPGA, it can be continuously upgraded and improved to achieve more functions. On this basis, the system can be further expanded, such as adding a single-chip microcomputer and transplanting an embedded operating system, replacing the digital tube with a dot-matrix liquid crystal, and adding external storage (flash, RAM, etc.), thus forming a handheld error code The test system can work completely out of the main control computer.

Responsible editor: gt

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