Through ep2c20q240 device and LPC2478 processor, this paper studies the working principle and timing characteristics of the external parallel bus of arm application system, as well as the principle of bidirectional bus design in FPGA, designs and implements the FPGA parallel bus. With the help of Quartus II simulation tool, the timing simulation of FPGA parallel bus is carried out, and the online test is carried out with signaltap II logic analyzer, Verify the correctness of the design

0 Introduction

In the design of digital system, FPGA + arm system architecture has been more and more widely used. FPGA mainly realizes high-speed data processing; Arm mainly realizes the system flow control, human-computer interaction, external communication and FPGA control. I2C. SPI and other serial bus interfaces can only realize the low-speed communication between FPGA and arm; When a large amount of data is transmitted and high-speed transmission is required, parallel bus is needed for high-speed data transmission between them

Next, based on ARM processor LPC2478 and FPGA device ep2c20q240, taking the read operation timing of arm external bus as an example, the parallel bus of high-speed transmission between them is studied; The data bus is 32 bits; A 1024x32bits SRAM high speed memory buffer is constructed in FPGA to facilitate ARM processor to read and write FPGA internal data quickly

The principle of arm parallel bus

The external parallel bus of ARM processor LPC2478 consists of 24 address buses, 32 data buses and some control signal lines such as read-write, chip selection and so on. According to the system requirements, the width of data bus can also be configured as 8-bit, 16 bit and 32-bit working modes

In this design, the signals of arm external bus are: cs.we.oe.data [310]. Addr [230]. BLS, etc

Design of arm parallel bus and port based on FPGA

According to the operation sequence of arm external parallel bus, the read and write operations of arm external bus are carried out when CS is low level effective. Because the read and write operations cannot be carried out at the same time, we and OE signals cannot appear low level at the same time

Data bus is a two-way bus, which requires FPGA to realize two-way data transmission. The restriction relationship between time sequences is given in the sequence diagram. When designing FPGA, it should meet the requirements of arm signal establishment time and holding time, otherwise the reading and writing may be unstable

Design of parallel bus based on FPGA

2.1 port design of FPGA

The block diagram of the external parallel bus connection between FPGA and arm is shown in Figure 2. Because the SRAM storage unit in FPGA is 32 bits, there is no need to select the byte group, so the BLS signal can not be connected. In order to realize the fast data transmission between arm and FPGA, the SRAM in FPGA has to read and write with ARM processor, It also exchanges data with other logic modules in FPGA, so SRAM uses dual port RAM

Design of arm parallel bus and port based on FPGA

From the aspect of port direction, data port is in out (bidirectional) mode, and other ports are in (input) mode. From the aspect of port function, clk20m is global clock, and FPGA global clock network should be adopted in implementation, which can effectively reduce clock delay and ensure the correctness of FPGA timing. Addr is a 16 bit address bus, Data is a 32-bit bidirectional data bus, and the design of bidirectional bus is the focus of the whole design. OE is the read enable signal input from arm to FPGA

We is the write enable signal of arm input to FPGA. CS is the chip select signal of arm input to FPGA. When FPGA is not selected by arm, it must output high resistance state to avoid bus conflict

2.2 design of bidirectional bus based on FPGA

In the parallel bus design of FPGA, if the top and bottom modules use bidirectional IO ports, the design principles should be followed; The design principle of bi-directional IO port is: only the top-level design can use the inout port. In the bottom module, the inout port at the top-level should be transformed into an independent in (input). Out (output) port and a directional control port should be added. The VHDL code of the top-level design is as follows:

Design of arm parallel bus and port based on FPGA

Among them, data_ i.DATA_ O and output_ EN is the internal signal of FPGA. In the internal modules of each level, one-way IO control can be carried out through these three signals. In this way, the bidirectional data port in the top-level design is transformed into the internal one-way data port_ I (input). Data_ O (output) and output_ In the internal modules, combining these three signals and addr.oe.we.cs and other signals, the function of arm bus interface can be easily realized

Design of arm parallel bus and port based on FPGA

3 Analysis of simulation results

The FPGA parallel bus is simulated by Quartus II; The simulation results are shown in Figure 3. According to the reading and writing sequence diagram of arm parallel bus, it can be seen from the simulation results that the bus interface design of FPGA meets the design requirements. Because the selected FPGA device has the function module of logic analyzer, the FPGA design module is tested online through the signaltap II logic analysis tool in Quartus II software, It is found that the bus timing meets the requirements of arm parallel bus and works stably. The correctness of the design and simulation results is verified from another point of view

Design of arm parallel bus and port based on FPGA

4 Conclusion

Because FPGA technology and arm technology are more and more widely used, the design of parallel bus interface to realize the data exchange between them can easily solve the demand of fast data transmission, so it is particularly important to design FPGA parallel bus to meet the system requirements, The system runs stably and has good performance. The above design and simulation methods can be used as reference for other similar designs

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