1. Introduction

Integrated system on chip (SOC) is an important direction of integrated circuit development. Due to the many advantages of digital signal processing and the improvement of digital integrated circuit performance and the decline of cost in recent years, digital circuit plays a more and more important role in SoC system. Because people always need to convert digital signals into corresponding physical quantities in the real world, digital to analog converter (DAC) has become an indispensable and important module in SoC system. With the continuous improvement of digital signal processing speed, the demand of SoC system for high-speed DAC is more urgent. High Speed DAC is widely used in many fields such as communication, measurement, automatic control, multimedia and so on, and its performance has an important impact on the overall performance of the system. The design of high-speed DAC is of great significance for the design of good high-performance SoC system.

This paper selects the deep submicron CMOS process widely used in SoC chip to realize a 10 bit high-speed DAC. The DAC can be used as an IP hard core in SoC design to realize reuse in system design in many different application fields.

2. Design of High Speed DAC

2.1 structure of High Speed DAC

The design of high-speed and high-precision DAC generally adopts current driven structure. Taking 10 bit current driven DAC as an example, its structure is shown in Figure 1.

Figure 1 structure diagram of 10 bit current driven DAC

In the current driven DAC, if the thermometer code is used internally to replace the binary code for switching control, the linearity and spurious free dynamic range (SFDR) performance of the DAC can be greatly improved. However, for current driven DAC with 10 bit or higher accuracy, if full thermometer code is used, the area and power consumption of decoding circuit will be too large. Most high-precision current driven DACs choose segmented coding structure to meet the needs of improving DAC performance and controlling the size of decoding circuit. The DAC design of this paper selects the 7 + 3 segmented coding structure, that is, the high 7 bits of the input signal are converted into thermometer code, and the low 3 bits are directly binary code.

2.2 design of high speed decoder

When the speed of DAC becomes faster and faster, the speed of thermometer code decoder often becomes the bottleneck of DAC speed. Although the traditional digital circuit design method is conducive to simplify the decoding circuit, it is difficult to achieve high-speed decoding, especially when there are many bits of the decoder [3]. In order to effectively design the high-speed decoder, this paper forms a unified synchronization circuit with the decoder and the delay device. According to the design principle of the synchronization circuit, the design of the high-speed decoder and the delay device is completed by using the automatic synthesis and layout tool.

The circuit structure of high-speed decoder and delay device is shown in Figure 2. The box marked’d ‘in the figure represents the D trigger triggered by the edge of the clock. As can be seen from Figure 2, the 7-bit thermometer code decoding circuit and the 3-bit binary code delay unit are placed between D flip flops, so that all input-output paths can clearly write timing constraints, which creates necessary conditions for the use of automatic synthesis tools. In this design, the specific design process of high-speed decoder and delay device is as follows: firstly, RTL code is written in Verilog HDL language; Then compile the timing constraint file, use the design compiler tool to complete the automatic synthesis of the decoder and delay circuit, get the gate level network list, and conduct the gate level post simulation; Next, silicon ensemble tool is used to complete the automatic layout and routing of standard units, and Pearl software is used for static timing analysis in the process of layout and routing; Finally, calibre software is used to check the DRC and LVS of the final layout to verify the correctness of the layout. Through the above design methods, a 7-bit decoder with a maximum decoding speed of 300MHz is realized.

Fig. 2 circuit structure of high-speed decoder and delay device

2.3 design of switching unit

The design of switching unit has an important impact on the performance of DAC at high speed. For a high-speed DAC design, not only the DAC is required to achieve high conversion speed, but also the DAC is required to achieve good performance at high conversion speed. Therefore, the design of switching unit plays an important role in the design of high-speed DAC.

Fig. 3 circuit diagram of current source unit and switching unit

The switching unit used in the DAC design in this paper is shown in Figure 3. The switching unit mainly includes two parts: synchronous latch and current switch. The main function of synchronous latch is to synchronize the switching of current switches in each switching unit of DAC with the clock, so as to minimize the output spurious caused by delay error. In addition, by adjusting the size ratio of ML3 and ml4 to ML5 and ml6, the synchronous latch can also adjust the intersection potential of the switch control signal (a pair of differential signals), so as to ensure that a pair of switches will not be turned off at the same time, so as to reduce the resulting output burr [4]. The synchronous latch in this paper connects the clock controlled MOS switches ML1 and ML2 in series before ml3-ml6, which reduces the requirements of the synchronous latch on the power supply voltage and is conducive to the realization of the circuit in deep submicron CMOS technology.

The current switch in the switching unit is composed of msw1-msw4. Compared with common current switches, adding msw3 and msw4 can play two roles: on the one hand, they reduce the burr voltage of the digital control signal directly fed to the output through the CGD of msw1 and msw2; on the other hand, they reduce the influence of the change of output voltage on the internal node voltage of the current source, so as to improve the SFDR performance of DAC under high-speed conditions from two aspects.

2.4 design of current source unit

The current source unit in this paper adopts a common source common grid current source circuit, as shown in Figure 3. The cascode current source can achieve high output impedance, which is not only conducive to improve the linearity of DAC in static operation, but also to improve SFDR. The size design of current source unit has an important impact on the performance of DAC. In the circuit shown in Figure 3, Mcs1 tube shall have enough area to ensure the matching accuracy between current source units to meet the requirements of 10 bit DAC linearity. In this paper, the Monte Carlo method is used to model the current source. It is calculated that if the yield of 10 bit DAC (the percentage of inl and DNL less than 0.5lsb) is greater than 99%, the mismatch between current source units must meet:

(1)

According to formula (1) and MOS tube mismatch characteristic formula (2) [5]

(2)

The minimum size of Mcs1 tube can be calculated. In equation (2)And

It is inversely proportional to the area of Mcs1 tube and calculated according to the specific process data provided by the chip manufacturer.

3. Simulation results

The DAC of this paper is designed in SMIC 0.18 μ M CMOS process and simulated with cadence’s spectre software. The simulation results show that the maximum sampling rate of the DAC can reach 300ms / S (all corner worst cases). Under the condition of 200ms / s sampling rate and 20.8mhz input signal (1.8V power supply voltage and TT corner), the spectrum of DAC output signal is shown in Figure 4. It can be seen from the figure that at this time, the SFDR of DAC can reach 66.27db, which is also close to the average result of SFDR under all corners. Under SS corner, the SFDR of DAC is the lowest, but it also exceeds 60dB.

Monte Carlo simulation shows that the percentage of inl and DNL of the DAC is less than 0.5lsb and more than 99%. The power supply voltage of the DAC is 1.8V, the maximum output voltage is 1.5vpp (differential), the power consumption is only 22.7mw when the sampling rate is 200ms / s, and the area of IP hard core is about 0.55mm2.

Fig. 4 output spectrum of DAC under 200ms / s sampling rate and 20.8mhz input signal (TT corner)

4. Conclusion

This paper presents a design of high-speed and high-precision DAC applied to SOC, and realizes the design of IP hard core in deep submicron CMOS process. The design has good performance at high speed, and the power consumption and area are small. It can effectively meet the application requirements of SoC system design in the fields of communication, measurement, automatic control, multimedia and so on.

The author’s Innovation:

By adopting the design principle of synchronous circuit and the design method of automatic synthesis, layout and wiring, a high-speed thermometer code decoding circuit is realized. By improving the switching unit and reasonably designing the size of cascode current source, the good linearity of DAC and good performance at high speed are ensured.

Responsible editor: GT

Tagged:

Leave a Reply

Your email address will not be published.