Chip design from system modeling, software and hardware division of labor, architecture exploration of chip hardware design, to system application software development and performance benchmarking are all important factors in determining chip functions. Therefore, whether it is a hybrid and heterogeneous chip verification environment construction, Or support chip architecture exploration, performance analysis, and software and hardware co-verification, which are worthy of design companies' key research and development, which can help companies make market segmentation and product differentiation in the fiercely competitive semiconductor market.

Before the advent of electronic design automation (EDA), designers relied on manual methods to design integrated circuits. Nowadays, with the continuous development of process evolution and technology, designers must rely on auxiliary software to complete the functional design, synthesis, verification, and physical design of very large-scale integrated circuit (VLSI) chips. Since the development of the integrated circuit industry, EDA has become an indispensable part.

At present, the world's top EDA companies are all international companies, and these international companies occupy the vast majority of the market. The development trend of the main EDA technology, while the domestic EDA companies are in the catching up stage.

TechSugar recently launched an "EDA special" interview to deeply discuss the challenges and opportunities facing the current EDA field, and analyze the development paths of domestic and foreign manufacturers. The interviewee in this issue is Lin Junxiong, CEO of Guowei Sierxin.

At the beginning of the month, Guowei Sierxin announced the completion of a new round of financing of hundreds of millions of yuan, which will be used to build a full-process digital EDA tool platform. It is reported that the EDA tool independently developed by Guowei Sierxin is an indispensable tool in the functional verification process of the very large-scale digital integrated circuit (VLSI) design process. Guowei Si Erxin's solution covers the complete process of chip design verification, from the early chip planning verification to the final software and hardware development verification, there are suitable solutions, currently serving more than 500 customers around the world.

As semiconductor technology continues to evolve, EDA companies face more challenges

As the complexity of chip design continues to increase and the time-to-market window continues to shrink, the difficulty of design and verification continues to increase, as does the cost. How to provide automated tools to assist in the completion of more complex designs and verifications in shorter development cycles has become a common challenge. Traditional software simulation has been unable to meet the requirements of chip verification. Different verification methodologies must be integrated, and appropriate tools must be used according to actual application scenarios.

In response to the existing challenges, Lin Junxiong, CEO of Guowei Sierxin, said that Guowei Sierxin has accumulated nearly 20 years of technology, developed industry-leading prototype verification tool solutions, and provided automatic compilation technology, hypergraph segmentation and A large number of EDA software algorithms such as time division multiplexing technology, timing analysis convergence technology, static and dynamic probe automatic injection technology, and rapid modification iteration (ECO) technology can map the design of chip developers to a large number of FPGA arrays to achieve high-speed Simulation runs. At the same time, the prototype verification tool provides powerful in-depth debugging and waveform analysis tools, which can help chip developers to capture the most hidden design defects (Bug). The prototype verification system also provides powerful software and hardware co-simulation tools and rich interface libraries ( IP ) for chip developers to realize system co-simulation (RTL/C) and fast online debugging (ICE), support in-depth software debugging as soon as possible, and realize chip tape-out and software release after completion.

Prodigy complete prototyping solutions address the need for a comprehensive solution that operates at any functional design stage, design scale, and multiple geographic locations

The combination of advanced technology and packaging is becoming more and more close, and it also brings higher efficiency and flexibility to chip design. For example, the advanced technology of memory and 3D stacking packaging have brought greater bandwidth, and multi-chip packaging is to integrate chips of different processes into a single chipset, which greatly reduces the chip area and reduces power consumption. All of these put forward higher and more complex requirements for the field of chip design verification. For EDA companies, it is necessary to further strengthen the integration with systematic verification IP, and under the existing software and hardware architecture, to invest more resources to create and integrate new methodologies to achieve a comprehensive system for advanced technology. Modeling to estimate system performance on a single chip.

Advanced packaging provides high-bandwidth die-to-die (Die-to-Die) interconnects, which can also be seen as a way to continue Moore's Law. Chiplets with higher logic density are achieved through chiplet interconnections on a plane, or even 3D Chiplet interconnections. But with it comes a bigger challenge. The chip design must adapt to the complex product form of different IP and different chiplet combinations, and the new chip design must also work well with the original chiplet IP quickly. In response to such requirements, the EDA industry has proposed a hybrid heterogeneous verification method. The mature Chiplet, RTL-Ready IP, and System Modeling IP can be modeled and verified in one system at the same time, and take advantage of the high-speed advantages of Chiplet and RTL-Ready IP. Supports flexible configuration capabilities of System Modeling IP.

In advanced process development, IP costs are also increasing. Lin Junxiong mentioned that EDA companies have strengthened the construction of an industrial ecosystem, such as establishing a domestic IP alliance and jointly developing a more agile IP evaluation platform. The chip design of advanced technology integrates more IP, such as central processing unit (CPU), graphics processing unit (GPU), artificial intelligence accelerator and high-speed interface, which all require corresponding verification VIP to ensure the correctness and interface of the chip compatibility. In order to comply with the trend of increasing IP/VIP costs, EDA companies and IP companies need to work together to establish an EDA/IP cooperation ecosystem and develop an agile design verification environment to help customers shorten chip design cycles and accelerate product launch.

In the post-Moore's Law era, heterogeneous computing architecture has gradually become the mainstream design of advanced process chips

Now that the semiconductor industry has entered the post "Moore's Law" era, EDA manufacturers pay more attention to the same-level design and verification methods, from RTL to GDS, through AI-assisted automation tools and software synthesis to obtain low-abstract gate-level design, and further complete physical design. Chip design from system modeling, software and hardware division of labor, architecture exploration of chip hardware design, to system application software development and performance benchmarking are all important factors in determining chip functions. Therefore, whether it is a hybrid and heterogeneous chip verification environment construction, Or support chip architecture exploration, performance analysis, and software and hardware co-verification, which are worthy of design companies' key research and development, which can help companies make market segmentation and product differentiation in the fiercely competitive semiconductor market.

Under the advanced technology, heterogeneous computing architecture is gradually becoming the mainstream of designing chips. Different computing units have different architecture designs and different processing methods for information flow. These require different verification methodologies for their characteristics. Lin Junxiong said: "For the needs of heterogeneous chip design verification, we propose a unified verification platform based on the verification cloud system, which integrates different solutions such as system modeling, software simulation, hardware simulation, prototype verification, and formal verification to achieve efficient and rapid verification. .These solutions use a unified compilation/control script and core database, chip developers can choose the most suitable solutions at different stages of the project life cycle, and smoothly migrate to better solutions as the project progresses, Reduce switching costs. In addition, leveraging a unified verification platform also ensures that verification tasks at various stages are completed in the same environment.”

In addition to continuing the model of the three giants, the development of the domestic EDA industry cannot stop innovation.

Internationally, the viewpoints of unilateralism, isolationism and two sets of science and technology systems restrict global technological exchanges and are not conducive to the healthy development of the global semiconductor industry. Lin Junxiong believes that the degree of globalization of the semiconductor industry chain is already very high. No independent country can fully realize an independent industrial chain. The concept of fragmentation of the global market is political demand rather than industrial demand. The industry needs to be open and cooperative. attitude, and hope that through international exchanges and cooperation, the development of the global industry can be improved.

The domestic EDA field is relatively weak. In Lin Junxiong's view, the main reason is that China has not continuously invested resources in the EDA field to continuously develop and build a market ecology. China has developed the EDA product "Panda System" since the 1980s. It started not much later than the United States, and the technological gap at that time was not as obvious as it is now. However, because of the lack of continuous investment in research and development and building a market ecology, China has lost its global presence. Opportunity to compete in the EDA field. The three major EDA giants (Synopsys, Cadence and Siemens' Mentor) have continuously invested resources in research and development, mergers and integrations, and industrial ecology for more than 30 years, thus forming an absolute monopoly on the market today. In addition to continuing the model of the three giants, the development of the domestic EDA industry also needs to continuously innovate, introduce new methodologies, and integrate cutting-edge technologies such as "AI" in order to have the opportunity to build its own competitiveness.

At present, China's chip companies are also growing rapidly, and the sales of Guowei Sierxin in China have also increased, but the growth rate is obviously not in the same order of magnitude as the growth rate of chip companies. Lin Junxiong said that there are three main reasons for the huge difference. :

Domestic EDA companies are generally small in scale, and none of them can provide customers with a full-process platform, resulting in a huge gap between demand and supply capacity;

The industrial ecology created by the three giants for more than 30 years has been very successful, making customers highly dependent;

Design companies need to weigh the cost and potential risks of switching EDA platforms, so most design companies are in a wait-and-see state for domestic EDA products.

The prosperity and development of China's semiconductor industry has indeed brought a lot of opportunities to domestic EDA companies. Lin Junxiong mentioned: "We need to correctly face the differences mentioned above, continue to invest in technology research and development and support, and strive to bridge the huge gap between supply and demand. , to attract domestic customers with more cutting-edge methodology, more effective provision of real-time technical support and remote collaborative development capabilities. At the same time, we also expect to work with domestic customers to jointly establish a domestic EDA industry ecology and promote the coordinated development of all links in the semiconductor industry chain. "

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