Frequency source is one of the core parts of modern electronic systems, such as communication system, radar system, instruments and meters. Its performance directly affects the stability of the whole system. There are many methods of frequency synthesis at present, among which direct digital synthesis (DDS) and phase locked frequency synthesizer (phase locked) are widely used Loop, PLL), but they have their own advantages and disadvantages. DDS has high frequency accuracy and spurious suppression, but wide bandwidth is the difficulty in its implementation; PLL has a high frequency output bandwidth, but the inevitable phase noise and spurious are its defects. The design of wideband stepped frequency signal source discussed in this paper combines the advantages of the two, which can produce the signal with low noise and high output bandwidth.
In recent years, wideband stepped frequency signal has been widely used in communication and reach system for its unique advantages. Therefore, this paper focuses on the design method of LS band broadband stepped frequency signal source. Considering the high system integration and timing control performance of FPGA, the spartan3 series FPGA of Xilinx company is used to configure and control the frequency source module, The output frequency of frequency source can meet the design requirements.
Working principle of 1 Frequency Synthesizer
The frequency synthesizer chip is ADF4350 of ADI company. The chip is a low noise spurious PLL (phase locked loop) chip which integrates VCO, phase detector, charge pump and frequency divider. VCO fundamental wave output frequency range is 2200 ～ 4400 MHz. It supports fractional and integer N-frequency division. Using 1 / 2 / 4 / 8 / 16 frequency division circuit at the output end, any frequency in the band of 137.5 ～ 4 400 MHz can be generated. The on chip VCO core is composed of three independent VCOs, whose output sensitivity is 33 MHz / v. each VCO uses 16 overlapping frequency bands. The frequency output of the whole frequency band can be controlled only through the voltage control range of 0.5-2.5 v. the chip is packaged in 5 mm × 5 mm package, which has the characteristics of high integration, strong reliability and low power consumption. Details of ADF 4350 can be found in the references.
The reference frequency Fref of ADF4350 frequency synthesizer is provided by the outside, and the frequency is provided to the phase detector after the internal R frequency divider, which is used as the reference frequency FPFD. The feedback frequency of RF output rfout is FN after passing through the internal n-divider. The phase detector converts the phase difference between FN and FPFD into proportional pulses and supplies it to the charge pump. The charge pump generates a push-pull current with error information, which is converted into a tuned voltage with phase difference information by integrating the loop filter outside the chip. The VCO voltage control terminal is tuned to control and output the corresponding frequency. The output frequency of VCO on chip is output by the output divider (1 / 2 / 4 / 8 / 16) circuit to generate the required RF output signal
Among them, int is the integer division value of the n-divider in the chip, frac and mod are the numerator and denominator of the fractional frequency division coefficient of the n-divider respectively, and the frequency division coefficient RFD of the RF output terminal is 1 / 2 / 4 / 8 / 16. Therefore, through FPGA configuration, the design of broadband stepped frequency signal source can be realized by regularly adjusting the frequency division value of FPFD or internal N frequency divider. ADF4350 hardware peripheral schematic diagram is shown in Figure 1.
Resistance R1 is used to select whether to use the fast lock mode of ADF4350. The specific resistance value is calculated by adisimpll simulation tool according to the loop bandwidth value. The system adopts the non fast stabilization mode, so the R1 resistance in the actual circuit is open circuit. The testability design of hardware circuit can facilitate the later system hardware debugging. Considering the circuit transmission characteristics of high-frequency signal, filter capacitors are added to each power supply and main pins, and the frequency output end is output in the form of double port difference, which improves the anti-interference characteristics of frequency output.
Parameter design of 2-step frequency source
The parameters of the broadband stepped frequency source discussed in this paper are as follows: the operating frequency range is 1.1-2.124 GHz, and the step frequency interval of RF output is 2 MHz, that is, 512 scanning frequency values are output in each step cycle. The output power is adjustable. The phase noise of single frequency point is better than – 90 DBC / [email protected] KHz, spurious is better than – 60 DBC.
Through hardware debugging, it is found that each time the n-divider is updated, the step frequency will be generated. Due to the difference of the frequency division value, the PLL inside the chip will be completely out of lock, and then it will be locked again after a period of time. During this period, the VCO voltage control terminal will appear larger jitter, extend the locking time, and the output spurious is serious. Therefore, this paper focuses on the following implementation scheme.
Fixed the value of ADF4350 internal frequency divider, by adjusting the FPFD, the RF output can produce broadband stepped frequency signal. DDS has high frequency resolution and short conversion time, but its bandwidth and maximum output frequency are limited. The PLL frequency synthesizer has high frequency and bandwidth, but its conversion time is relatively long. Therefore, the scheme combines the two and combines their advantages to obtain high performance frequency output. The frequency division value of the internal register does not change with the change of the step frequency. Therefore, the locking time of the phase locking loop is very short, and the frequency output spurious suppression is good, which meets the design requirements. The overall implementation block diagram is shown in Figure 2.
Set the frequency division parameter in R divider of ADF4350 frequency synthesizer to 0. The reference frequency of phase discrimination is equal to the external reference frequency, that is, Fref = FPFD. The system is set to work in low noise mode, the RF output divider is set to 2 frequency division, and the feedback terminal is set as VCO fundamental frequency. The DDS chip used in this scheme is AD9850, which is a low cost and low phase noise chip of ADI company
Phase is the value of phase accumulator and CLKIN is the reference input frequency of DDS. The reference frequency of DDS in this paper is provided by FPGA internal digital clock management unit DCM through 6-fold frequency output, which is 120 MHz.
According to the design requirements of frequency output parameters, the internal frequency divider value of frequency source chip is set as int = 160, frac = 0, mod = 20. Then formula (1)
It can be seen that:
Therefore, in order to enable rfout to output a scanning signal with a bandwidth of 1.1-2.124 GHz and in steps of 2 MHz, the corresponding scanning frequency range of FPFD is as follows:
FPFD = (1.1-2.124) GHz / 80 = 13.75-26.55 MHz, step interval is; △ FPFD = 2 MHz / 80 = 25 kHz
Since R divider does not participate in frequency division and frequency multiplication, there are FDDS = Fref = FPFD, △ FDDS = △ FPFD. It can be seen from formula (2)
To sum up, the phase configuration data should be 492 131 669-950261 514, and the data update interval is 894785. All the configuration data of phase are calculated by MATLAB software, and the output of ADF4350 can be controlled to produce broadband step frequency signal by configuring DDS with a certain timing sequence through FPGA.
3 test results
ADF4350 has two channels of RF output. Considering the scalability of the system, the main output is converted to single port mode and transmitted to the next level. The auxiliary RF output is designed as differential output mode, which is convenient for system function expansion. The circuit adopts 3.3 V single power supply, and the actual PCB is shown in Figure 3.
The VCO voltage control terminal is tested by oscilloscope. Under the condition of 100 kHz loop bandwidth, voltage jitter is displayed by 10 times voltage amplification, as shown in Fig. 4. The lock-in time is about 12 μ s.
Through the FSP spectrum analyzer of R & S company, the single frequency and step frequency are tested. The RF output power is + 1 DBM through FPGA programming. The output power and phase noise are tested. The test results are listed in Table 1.
The single point frequency output is 1.5 GHz, the span width of spectrum analyzer is 50 MHz, the output power is 0.22 DBM, and the phase noise is -93.83 [email protected] The test results are shown in Figure 5.
Configured by FPGA, the holding time of each step frequency point is set as 100 μ s, and the power value of broadband step frequency is tested through spectrum analyzer. The results are shown in Fig. 6.
According to the test results, all indexes of the scheme design basically meet the design requirements. Due to the attenuation and reflection of transmission line, the output power of step frequency scanning is not stable enough. The back stage of the broadband stepped frequency source designed in this paper can expand the network of digital attenuator, amplifier and frequency selective filter, which will be conducive to adjusting the output power stability and suppressing the out of band spurious.
The LS band wideband stepped frequency signal source designed by this method combines the advantages of DDS and PLL chip, and achieves the required frequency source design requirements under the comprehensive configuration and control of FPGA. If the reference voltage update frequency of VCO is set according to its 16 overlapping frequency band, that is, the whole frequency output only updates the reference voltage for 16 times, then in the linear range of single VCO, the stability time of output frequency will be nanosecond level, and this method will be focused on in the later design. The broadband stepped frequency source designed by this method has the characteristics of high integration, good frequency stability, simple circuit and low power consumption. At the same time, as the frequency source of general electronic equipment, the frequency source can output 135 MHz ~ 4.4 GHz bandwidth output through FPGA configuration, which has a wide range of engineering practical value.