The digital phase locked loop has been widely used in the fields of digital communication, radio electronics and power system automation. The traditional all-digital phase-locked loop (DPLL) is composed of medium and small-scale TTL integrated circuits. This type of DPLL has a low operating frequency and poor reliability. With the development of integrated circuit technology, not only can a high-frequency monolithic integrated phase-locked loop be made, but also the entire system can be integrated into one chip to realize the so-called system on a chip (SOC). Therefore, the all-digital phase-locked loop can be embedded in the SOC as a functional module to form an on-chip phase-locked loop. The following introduces a scheme of designing DPLL using VHDL technology.

1. Working principle

The structural block diagram of the all-digital phase-locked loop is shown in Figure 1.

The digital phase detector is composed of XOR gates, the digital loop filter is composed of a variable-mode reversible counter, and the numerically controlled oscillator is composed of an add/subtract pulse controller and a divide-by-N counter. The clock frequencies of the reversible counter and the up/down pulse controller are Mf0 and 2Nf0, respectively. Here f0 is the center frequency of the loop, and in general M and N are integer powers of 2. The clock 2Nf0 is obtained by dividing the counter by H (=M/2N). The corresponding waveform of the time limit is shown in Figure 2.

When the loop is trivial, u1 and u2 are in quadrature, the output signal ud of the phase detector is a square wave with a 50% duty cycle, and the phase error is defined as zero at this time. In this case, the cycle of “adding” and “subtracting” of the reversible counter is the same. As long as the k value of the reversible counter is large enough (k>M/4), the output end of the reversible counter will not generate carry or borrow pulses. At this time, the add/subtract pulse controller only divides the frequency of its clock 2Nf0 by two, so that the phases of u1 and u2 are kept in quadrature. In the case that the loop is not locked, if ud=0, it makes the up-down counter count up, and causes the carry pulse to be generated. A half clock cycle is added to the divide-by-2 process. On the contrary, if ud = 1, the reversible counter counts down, and will send a borrow pulse to the “minus” input terminal d of the add/subtract pulse controller, so the controller will subtract half in the process of dividing by two. cycle. This process happens continuously. After the output of the plus/minus pulse controller is divided by the N counter, the phase of the local estimation signal u2 is adjusted and controlled, and finally the locked state is achieved.

2. Design of loop components

The focus here is on the design of the digital loop filter. The digital loop filter is composed of a variable-mode reversible counter. Under the control of ud, when j=0, the clock Mf0 is counted “up”; when j=1, it is counted “down”. The counting capacity (modulus k) of the reversible counter can be preset by using the four bits of A, B, C and D, so that the modulus can be changed easily. The range of the preset modulus is, when D, C, B, and A take values ​​in the range of 0001 to 1111, the change range of the corresponding modulus is 23 to 217. It can be seen that the length of the reversible counter can be controlled by digital programming according to the size of the modulus k value. When D, C, B, and A are taken as 0001, K=23, and the length of the counter is only three levels, so the capture band can be expanded and the locking time can be shortened. When D, C, B, A take 1111, K=217, the length of the counter becomes seventeen levels, at this time, the capture zone is reduced, and the shortening time is prolonged. The VHDL design program of the variable-mode reversible counter is as follows:

library ieee?

use ieee.std_logic_1164.all?

use ieee.std_logic_unsigned.all?

enTIty count_k is

port clk j en d c b a in std_logic

r1 r2 out std_logic ?

end?

architecture behave of count_k is

signal cq k mo std_logic_vector 16 downto 0 ?

signal cao1 cao2 std_logic?

signal instrucTIon std_logic_vector 3 downto 0 ?

begin

instrucTIon<=d & c & b & a?

with instrucTIon select mo <=″00000000000000111″ when ″0001″?

″00000000000001111″ when ″0010″?

″00000000000011111″ when ″0011″?

″00000000000111111″ when ″0100″?

″00000000001111111″ when ″0101″?

″00000000011111111″ when ″0110″?

″00000000111111111″ when ″0111″?

″00000001111111111″ when ″1000″?

″00000011111111111″ when ″1001″?

″00000111111111111″ when ″1010″?

″00001111111111111″ when ″1011″?

″00011111111111111″ when ″1100″?

″00111111111111111″ when ″1101″?

″01111111111111111″ when ″1110″?

″11111111111111111″ when ″1111″?

″00000000000000111″ when others?

process clk en j k cq

begin

if clk'event and clk='1' then

k<=mo?

if en='1' then

if j='0' then

if cq<k then cq<=cq+1?

else cq<=?others=>'0' ?

end if

else

if cq>0 then cq<=cq-1?

else cq<=k?

end if?

end if

else cq<=?others=>'0' ?

end if

end if

end process?

process en j cq k

begin

if en='1' then

if j='0' then

if cq=k then cao1<='1'?

else cao1<='0'?

end if

cao2<='0'?

else

if cq=″00000000000000000″then cao2<='1'?

else cao2<='0'?

end if

cao1<='0'?

end if

else cao1<='0'? cao2<='0'?

end if?

end process?

r1<=cao1? r2<=cao2?

end behave?

According to the functional analysis of other loop components, the corresponding VHDL program can also be designed.

3 Design implementation

In this design, the all-digital phase-locked loop adopts the Foundation 3.1 version of XILINX Company to design, and realizes it with the FPGA of Spartan2 series. The simulation waveforms of the variable-mode reversible counter and the up/down pulse controller are given below, respectively, as shown in Figure 3 and Figure 4.

It can be seen from Figure 3 that when j=0, the reversible counter counts up. If the modulo k=24 is taken, then when the count value cq=0000FH, the counter generates a carry pulse (r1=1); when j=1, the When the rising edge of the next clock arrives, the reversible counter starts to count down, and when cq=00000H, a borrow pulse (r2=1) is generated. Changing the modulo k can lengthen or shorten the time for the reversible counter to generate carry pulses and borrow pulses. At the same time, it can be seen from Figure 1 that the up/down count signal j of the reversible count is controlled by the output signal ud of the phase detector, and its carry pulse r1 and borrow pulse r2 are respectively connected with the i and i of the add/subtract pulse controller. d is connected to control the sequence of its output pulses. As can be seen from Figure 4, when there is no carry and borrow pulses, the add/subtract pulse controller divides the 2Nf0 clock by two. Once the reversible counter has carry pulse or borrow pulse output, it acts on the i or d end of the add/subtract pulse controller, and the output pulse sequence changes. When the reversible counter outputs a carry pulse, let i=1, then after the falling edge of i, a pulse is inserted into the output terminal q of the add/subtract pulse controller, that is, a half cycle is added to its output sequence; otherwise , when the reversible counter outputs a borrow pulse, let d=1, then after the falling edge of d arrives, the q terminal deletes a pulse, that is, half a cycle is deleted in the output sequence of the add/subtract pulse controller. From the above analysis of the simulation waveforms in Figures 3 and 4, it can be seen that the logic functions of the variable-mode reversible counter and the plus/minus pulse controller meet the design requirements. Connect all the components of the all-digital phase-locked loop for system simulation, and the simulation waveforms are shown in Figure 5 and Figure 6.

Among them, Fig. 5 is the system simulation waveform when k=25 is taken. It can be seen from the figure that the simulation time when u1 and u2 reach the locked state is 175 μs. Figure 6 is the system simulation waveform when k=28. In this case, the simulation time when u1 and u2 reach the locked state is 1.04ms. Obviously, the larger the modulo k, the longer the loop takes to enter the locked state.

It is worth pointing out that in the locked state of the loop, carry and borrow pulses will be generated due to the continuous counting of the reversible counter or under the interference of noise. If the value of k is made too small, the up-and-down counter will generate carry or borrow pulses due to frequent cyclic counting, which leads to phase jitter at the output of the loop. To reduce this phase jitter, the value of k must be greater than M/4.

It can be seen from the above analysis that the value of the modulus k should be appropriate. If k is large, it is beneficial to suppress noise and reduce phase jitter, but at the same time, it increases the time for the loop to enter the locked state. Conversely, if k is small, the locking of the loop can be accelerated, but the ability to suppress noise is reduced accordingly.

Using VHDL to design an all-digital phase-locked loop has the advantages of flexible design, convenient modification and easy implementation, and can be made into an embedded on-chip phase-locked loop. The modulus of the counter in this type of digital phase-locked loop can be modified at will. In this way, the loop can be designed maximally and flexibly according to different situations.

Responsible editor: gt

Leave a Reply

Your email address will not be published.