In the field of control, PID control is one of the earliest control strategies. Because of its simple algorithm, good robustness and high reliability, it is widely used in industrial process control. In addition, with the development of control theory, the combination of expert system, fuzzy logic, neural network, grey system theory and traditional PID control strategy has derived a variety of new PID controllers, forming a huge PID family. Many algorithms have greatly improved the performance of traditional P1D controller. However, the practical application of these algorithms in industry is far behind the traditional PID algorithm. One of the reasons is that the complexity of the algorithm makes the hardware design and debugging more complex, or makes the software code lines increase and the delay increase, The development cycle becomes longer. Stability and reliability have become an important issue in the design of new systems.
In recent years, with the rapid development of microelectronics technology, the level of integrated circuit design and technology has been greatly improved. With the development of ultra deep submicron technology, it is possible to integrate the electronic system composed of many ICs on a single silicon chip, forming the so-called system on chip (SOC), and promoting the vigorous development of the corresponding EDA tools.
With the great abundance of control algorithms and the rapid development of microelectronics technology and EDA tools, we can integrate the application advantages of the two fields. With the help of EDA tools, we can quickly and easily implement various new algorithms on FPGA, and complete the design of the whole control system from the behavior algorithm level (system level) to the physical structure level, So as to achieve a variety of new PID algorithm is widely used in the actual industrial control system.
2. Discrete PID control algorithm
2.1 PID algorithm
Proportional integral differential (PID) control is the most mature and widely used control method in the control system. The basic principle is that according to the deviation value of the feedback control system, the operation is carried out according to the relationship of proportional, integral and differential functions, and the results are output to the actuator, which controls the controlled object according to the calculation results of the deviation value. In continuous time domain, the expression of PID controller algorithm is as follows
Where e (T) is the input of the controller, that is, the deviation between the given quantity and the output of the control system; U (T) is the output of the controller; KP is the proportional coefficient; TL is the integral time constant; TD is the differential time constant.
2.2 discretization of PID algorithm
Because the computer control can only calculate the control quantity according to the deviation value of sampling time, it is necessary to discretize the above formula. According to the analog PID control algorithm formula (1), a series of sampling time points KT represent the continuous time t, the rectangular method numerical integration (sum formula) is used to approximate the integral, and the first-order backward difference (increment) is used to approximate the differential
The expression of discrete PID is obtained
Where, the integral coefficient K1 = KP / TL, the differential coefficient Kd = kptd, t is the sampling period, K is the sampling sequence number, k = 1,2,…, e (k-1) and E (k) are the deviation signals obtained at the (k-1) and k th time respectively.
2.3 PID control system block diagram
The PID control block diagram of general control system is shown in Figure 1. Where, source is the set value of the system, feedback is the feedback value of the system, e (T) is the feedback error, and U (T) is the output value of the PID controller. The “PID control algorithm” block diagram subsystem in the figure requires us to use DSP Builder for top-down design simulation at the algorithm level.
3. FPGA design steps and development of PID control system based on DSP Builder
3.1 a1tera DSP Builder component of Simulink toolbox
In the development and application of the system using FPGA, there is a new design tool and design process. DSP Builder。 Altera is a system level tool for chip level development such as DSP. As a tool box of MATLAB, it makes it possible to design a special chip system with FPGA through the graphical interface of Simulink, as long as the modules in DSP Builder toolbox are simply called. It is worth noting that the basic modules in DSP Builder are described at the algorithm level, which is easy for users to understand from the system or algorithm level, and even do not need to know the FPGA itself and hardware description language very well. This provides a convenient condition for engineers in the field of traditional control system to develop the top-down algorithm level design of reliable control system chip based on FPGA / ASIC.
3.2 using DSP Builder to complete the top-level algorithm design in MATLAB
The design method can start from the system level which has nothing to do with hardware. Firstly, the top-level system design and system simulation test are completed by using the powerful system design and analysis ability of MATLAB and the modules (or IP core) provided by DSP Builder.
According to the principle of Figure 1, the design simulation is carried out in MATLAB, and the top-level design model of Simulink is shown in Figure 2.
In the top-level design model, in addition to “PID control subsystem”, other parts are designed with general Simulink components. In order to be more close to the actual system in the verification and simulation, a delay with adjustable delay depth is added to the controlled object. The signal generator gives the system setting value. For the general practical control system, the typical rectangular wave can be used. Here, the superposition of several rectangular waves and sine waves is used to simulate the system setting value.
The “PID control subsystem” in the model realizes the PID algorithm part. After the simulation design, the subsystem will be converted into FPGA HDL language design through the signal compiler in DSP Builder, so this part needs to be designed with DSP Builder components except the oscilloscope needed for simulation observation, otherwise the signal compiler cannot recognize when compiling.
In order to simply explain how to use DSP Builder to design the control system based on FPGA from top to bottom, this paper uses the ordinary position type PID algorithm as an example. The design block diagram of PID control subsystem of position PID algorithm is shown in Figure 3.
In Figure 3, the input error signal adopts 16 bit precision. In order to realize the precise adjustment of proportional, integral and differential coefficients, the PID coefficient adopts 8-bit precision, so that the coefficient can be at least accurate to the percentile. At the same time, in order to avoid the floating-point number operation, the PID coefficient is taken as an integer, and the data value is amplified to 24 bits. After the parallel adder operation unit, the bus converter unit in io & bus is used to convert the accumulated data into bits to realize the floating-point number operation in FPGA.
Matlab simulation results are shown in Figure 4. Where, source is the set value of the system and feedback is the feedback value of the system.
After the waveform simulation is successful, the graphical top-level design model in MATLAB needs to be transformed into HDL language description file which can be recognized by FPGA development software. In Figure 2, by opening the signal compiler module and configuring relevant parameters, the “PID control subsystem” designed by DSP Builder can be compiled into RTL expression of VHDL and veirlog language and TCL script of tool command language. According to the design model in front of the compilation information, until the three states of convert MDL to VHDL, synthesis and Quartus II fitter in the compilation report are passed, the TB required by Modelsim can be obtained_ Systemname.tcl function simulation file script and systemname.qpf project file and systemname.vec simulation waveform file required by quartus.
3.3 implementation of HDL code function simulation in Modelsim
In the Modelsim menu, execute macro in tools 1 to open the signal compiler generated file TB_ System name.tcl (vhbl) or TB_ vo_ Systemname. TCL (Verilog). After successful debugging, the simulation results are shown in Figure 5. The function simulation results are basically consistent with those in MATLAB, which proves that the top-level design is basically successful.
3.4 FPGA development in quartus
Open the signal compiler generated file systemname.qpf in quartus. Set the corresponding device and run systemname in TCL scripts_ Quartus.tcl configures the project variable and compiles. After successful debugging, load systemname.vec waveform simulation file, run the timing simulation tool, and get the result in Figure 6, which is basically consistent with figure 5, which proves that the design is successful.
This paper presents the application of DSP Builder, a system level design tool originally used in FPGA, in the field of automatic control. At present, there is no relevant literature about the application of this cross field in the published domestic journals and paper library.
In the field of control, when a variety of complex new PID algorithms are applied to the actual control system, due to the limitations of the traditional single chip microcomputer and discrete component circuit system, the new application and research and design progress is slow due to the hardware index and software complexity; The common FPGA / CPLD has some disadvantages such as long cycle and poor reusability. We apply the increasingly perfect SoC design tools to the field of automatic control. We not only have new convenient and fast design tools in algorithm design, but also can solve the problems of electromagnetic interference and high system complexity existing in single chip microcomputer and discrete components by virtue of the advantages of FPGA hardware itself, Therefore, the feasibility of applying various new PID algorithms to practical industrial control system is greatly improved.
Further discussion in the system design: since the design starts from the MATLAB system level simulation which is completely independent of hardware, it is convenient for engineers in the traditional control field to quickly apply the idea of algorithm level to the design of control system, so that they can focus their limited energy on the design of system level algorithm and avoid falling into the repetitive and tedious circuit design, Shorten the time cycle from human brain conception to actual system implementation. A single design MDL file can even be packaged as an “algorithm package” for resource reuse, so as to realize the convenient increase or decrease of functional units and shorten the product development time. There may be interface standards for reusable algorithms and corresponding “packages” in the control field. This situation may be similar to the phenomenon of IP core in SoC field, which will not be discussed in this paper.
Editor in charge: GT