Arbitrary waveform generator (AWG) plays an important role in the field of radar and communication, but at present, most AWG use static memory. This makes it difficult to make the storage depth of waveform very large when the working frequency of arbitrary waveform generator is increasing, so it can not accurately express the complex signal. The design based on dynamic memory (SDRAM) introduced in this paper can effectively solve this problem, and a simplified design method of SDRAM controller is discussed in detail.
1. General scheme of arbitrary waveform generator
Working frequency, resolution and storage length are the three key performance parameters of arbitrary waveform generator. High working frequency means high output signal frequency and bandwidth, high resolution usually means high signal-to-noise ratio, and the storage length determines the accuracy of the signal. The scheme described below is an arbitrary waveform generator / card (as shown in Figure 1) developed in practice. Its working frequency is 300MHz, resolution is 14 bits, and storage length is 8m words. It has been widely used.
The circuit has two working states: write data state and read data state. The following is a brief description of its working process.
Write data status: CPU calculates the waveform data according to the waveform to be designed, and converts it into 14 bit unsigned number; turns on the bus switch, shields FIFO operation, and writes the waveform data into sdram1 and sdram2 alternately through the interface circuit with the cooperation of SDRAM controller, that is, sdram1 stores data 0, 2, 4, 6 in turn.. Data 1, 3, 5 and 7 are stored in sdram2.. (as shown in Table 1).
Read data status: turn on FIFO channel, turn off bus switch to disconnect the data connection between SDRAM and CPU; under the control of SDRAM controller, read the data in sdram1 / 2 at the same time (in parallel); after buffering by FIFO, get continuous data stream, and then convert from 32-bit to 16 bit parallel serial, increase the data rate by 2 times, supply DAC for digital to analog conversion, then get the edited data It’s a good signal.
In Figure 1, two SDRAM are used to work in parallel, because it is impossible for a single SDRAM to provide 300msps data stream. The actual device used is k4s641632c-tc60, and the working clock is 166MHz. FIFO caches the output data of SDRAM and converts the burst data stream into continuous data stream, so that the normal data output can be maintained when SDRAM is in refresh state. The actual device used is two parallel working idt72v263l6pf, the write clock is 166MHz and the read clock is 150MHz. The function of parallel to serial conversion is to improve the data rate, which is completed in the DAC device. The author uses ad9755ast with good dynamic performance. CPU and control interface is an ISA device based on PC, which can be improved to PCI device; clock circuit is used to generate 166MHz and 150MHz synchronous clock. The following focuses on the design of SDRAM controller, which is one of the main features of the system.
2. Design of SDRAM controller
2.1 main features of SDRAM
Compared with SRAM, SDRAM has larger capacity (usually several times to dozens of times); compared with DDR SDRAM or RDRAM, its control is relatively simple, so it is still a good choice for large capacity memory project. Several important basic concepts described below reflect its main features.
Row and column address: the address of SDRAM is row and column multiplexed, which effectively reduces the pins of the chip.
Precharge: read and write operations are only valid for precharged rows. That is to say, when the data read-write operation is across lines, it is necessary to perform at least one precharge operation first.
Automatic refresh: as we all know, as long as it is dynamic RAM, there is a refresh problem, SDRAM is no exception. Generally, all storage units need to be refreshed every 64ms.
Self refresh: when you need to keep the data in the chip, but do not need to operate temporarily, you can set the chip to enter the self refresh state.
Working mode register: the register that controls the working mode of SDRAM (as shown in Table 2).
2.2 state flow of SDRAM
The complete state machine of SDRAM consists of 17 states, and the state transition is non random (as shown in Figure 2). It is so many states and their complex transition relations that make the control of SDRAM more complex.
It should be noted that the state transfer of SDRAM can be divided into automatic transfer and manual transfer (the thick and thin arrows are shown in Figure 2). Automatic transfer enters the next state immediately after the end of the current state, while manual transfer stays in the current state after the end of the current state, and only one command allowed by the current state can enter the next state.
It can be imagined that it is not easy to design such a complex control process. Fortunately, a complete state machine is not needed in most applications. A simplified SDRAM state machine is discussed below.
2.3 simplified state flow
According to the characteristics of arbitrary waveform generator, the functions of SDRAM are simplified as follows
(1) The random access function is omitted, and it is fixed to read and write in sequence;
(2) The functions of standby, self refresh and normal read / write are omitted;
(3) Omit all pending functions;
(4) The working mode is fixed as burst read and single write;
(5) The data delay is fixed to 3 clock cycles;
(6) The refresh mode only uses the automatic refresh mode, and the device is in the continuous automatic refresh state when it is idle;
(7) The device is initialized only once after power on, and the working mode cannot be changed;
(8) The burst mode is fixed as sequential mode, and the burst length is fixed as whole page;
(9) Only read / write instructions with pre charge are used; an automatic refresh cycle is started after each read / write operation.
The simplified state machine is shown in Figure 3.
2.4 EPLD implementation of SDRAM controller
In order to realize the above simplified SDRAM control function, an EPLD device max7256atc144-6 produced by Altera company is used. Fig. 4 is a schematic diagram of SDRAM control flow of arbitrary waveform generator. As many details are involved in the specific programming, the main functions are as follows:
(1) Through ISA bus, the interface with CPU is realized to receive waveform data and read command;
(2) Power on automatic initialization;
(3) The linear address of 23 bits (8m word memory space) is generated and output in row column multiplexing mode;
(4) The control signal of SDRAM is generated to complete the functions of reading, writing and automatic refresh;
(5) FIFO is controlled to solve the problem that SDRAM refresh and waveform length are not multiple of page length.
Although it is quite complicated to fully apply SDRAM, it is completely feasible to design SDRAM controller with special requirements and suitable for specific conditions as long as its functions are reasonably simplified according to the principle of “enough is enough”. At present, the arbitrary waveform generator based on SDRAM has been applied to many R & D projects.
Editor in charge: PJ