1. Introduction

In the design of GPS receiver, in order to test and improve the signal processing algorithm, it is necessary to obtain GPS digital IF signal data locally. Using real data is not the best choice, mainly because many of the signal properties can not be controlled, and can not simulate different receiving environment and interference conditions, which brings trouble to the verification test of the algorithm; moreover, storing the real GPS data requires a lot of hardware resources. An effective way to solve this problem is to design a simulation signal source which can generate GPS digital IF signal and its parameters can be controlled.

The common design methods of simulation signal source are divided into two kinds: pure hardware mode and pure software mode. Pure hardware design is to use hardware devices and hardware expression to design directly, which is difficult and has a long period. Moreover, the change of system structure design will bring huge hardware design workload. The pure software design of the simulation signal source is to use software language to build the whole system on the PC, and the data generated need to be cached for hardware testing. This is not only a waste of storage resources, but also difficult to meet the real-time requirements. This paper introduces a new FPGA design scheme of GPS IF signal source. It uses Xilinx system generator for DSP tool to automatically convert system level expression into FPGA hardware expression, and completes the integration process from software graphic design to FPGA hardware implementation. Its advantages are that the function design part is completed in Matlab / Simulink, the structure of signal source is clear, the signal verification detection and parameter change are carried out; when the hardware is implemented, the optimized hardware description language file and hardware test file are automatically generated by Xilinx system generator tool, supplemented by Xilinx The hardware development platform greatly reduces the direct hardware design workload, shortens the process from design to implementation, and also facilitates the modification and upgrade of the system design.

2. Xilinx System Generator for DSP

Xilinx system generator is a FPGA aided design tool developed by Xilinx company, including Xilinx block set embedded in Simulink and model to hardware conversion software. It can automatically generate command files for FPGA synthesis, simulation and implementation tools. Users can complete the hardware development of the system model in the graphical environment. In the design, System Generator maps the modules in the Xilinx module collection into modules in the IP (Intellectual Property) library, then deducts the control signals and circuits from the system parameters, then converts the Simulink’s hierarchical design to VHDL’s hierarchical netlist, and then calls Xilinx Core Generator. And VHDL simulation, integrated implementation tools to complete the hardware design, and finally through FPGA platform to achieve the hardware system. In this way, the designer can easily transform from an abstract system level representation to a single source gate level FPGA hardware representation. It also solves the problem that the designers who are not familiar with the hardware language description carry out the hardware design and implementation.

3. FPGA design of GPS digital IF signal source

3.1 GPS digital IF signal

Design and implementation of FPGA based on GPS IF signal source

3.2 design scheme

Figure 1 design scheme of GPS digital IF signal source

According to the generation formula of GPS digital IF signal, we can get the design scheme as shown in Figure 1. Each channel is responsible for generating the spread spectrum code, navigation data and other signals of a specific satellite (corresponding to a specific satellite PRN number). The parameter setting module is responsible for calculating and setting the key parameters of each module (such as satellite PRN number, carrier frequency, register status of code generator, etc.), including a Z counter and a X1 counter corresponding to GPS time. The carrier generator is based on NCO (numerically controlled oscillator) module in Xilinx module set. Its frequency and phase can be controlled by parameter setting module. The multipath module can simulate the multipath effect in the process of propagation. In the scheme, the signal generated by one or more satellites in the front end is added to the original signal after different delays. According to the different modules (C / a code acquisition or P code acquisition), different parameters (filter bandwidth and sampling rate) can be used in software design, or different hardware filters and samplers can be used in hardware implementation. This paper introduces the design of C / a code, P code generator, setter and other key modules.

3.2.1 design of C / a code generator and setter

The C / a code of GPS is gold code with sequence length of 1023, code rate of 1.023 MHz and period of 1 ms. The shift polynomials of the two 10 bit shift registers G1 and G2 are obtained by XOR combinationand

In this scheme, the C / a code setter can work in two modes

1) It is set at the initial point or half point of the code cycle period. According to the counter value corresponding to the target GPS time to be set, the chip number of the initial point or half midpoint of the cycle cycle of the nearest C / a code is converted, and the initial value of the inverted counter is set with this value. When its count is zero, the C / a code Setter will reset the G1 and G2 registers to their initial state or half midpoint state. Since then, the C / a code generator and the target GPS time synchronization. The maximum delay of the setting process is 511ms

2) Instant setting. In this scheme, a setting unit is designed for each register bit, which can be set to 0 or 1 when the next clock cycle comes. In this working mode, the module needs to first convert the C / a code status index corresponding to the target GPS time, and then find the register states of G1 and G2 by combining with the pre stored register status table, and modify the status by setting the unit in the next clock cycle. This mode enables instant synchronization.

3.2.2 design of P code generator and setter

The P code of GPS is obtained by combining the results of four 12 bit shift registers x1a, x1b, x2a and x2b with different characteristic polynomials. The phase precession of x1b relative to x1a, x2b to x2a, x2a / x2b to x1a and x2a / x2b to x1a / x1b are realized by decoding truncation, delay and clock control modules, so as to generate X1 epoch with period of 1.5 seconds and P code sequence with period of 38 weeks. By controlling the delay relative to the result, the purpose of generating different satellite corresponding P codes is achieved.

Figure 2 flow chart of x2b state setter

P code setter is more complex than C / a code setter. It needs to be designed according to different situations of 4 shift registers and reset at different time. Figure 2 shows the design algorithm of x2b register setter proposed by us. The design ideas of x1a, x1b and x2a are similar. X1 count, Z count and satellite PRN are input. Firstly, according to the count values of X1 and Z, the count value x2 in the X2 epoch and the count value x2b in a x2b cycle are calculated. If this time is in the last cycle of x1a of a week, x2b needs to be truncated at the end of this cycle. Otherwise, according to the different situations of x2b register corresponding to the set time, the number of P-code chips (N2b) to wait for from the initial state of the next register is calculated. When the count is zero, the x2b register is set to the initial state. From this moment, the status of the register is synchronized with the target GPS time. When the algorithm is implemented, the mcode module in Xilinx module set is used to write the algorithm program. The maximum delay of this algorithm is less than 500. Similarly, the P code setter can also work in real-time setting mode.

3.2.3 navigation data module

The navigation data is a 50 Hz binary code, which is composed of 12.5-minute-long superframes. Each superframe is divided into 25 frames, each frame has 5 subframes, each subframe is 10 words long, and each word length is 30 bits. The first, second and third frames of each frame broadcast satellite clock correction parameters and broadcast ephemeris, and the fourth and fifth subframes are almanac data, ionospheric correction parameters and other system information. In the scheme, we only design the first and second subframes. For the other three subframes, we convert the 24-hour GPS almanac data downloaded from NASA website into binary bit files and import them into navigation data module. The first subframe is a telemetry word (TLW), the first eight bits are synchronization header (10001011), the 9th to 24th bits are Satellite TT & C information and reserved bits (we set them to 0 here), and the last 6 bits are check bits. The second subframe is a handshake word (how), which is composed of Z count (counting the number of X1 epoch in P code generator), alarm flag, anti deception flag, subframe ID, reserved bit and check bit.

In the implementation, Xilinx mcode module and ephemeris data file can be used to generate simulation navigation data, and the external input interface can be designed to connect the real navigation data or the output of other navigation data simulator.

3.2.4 Gaussian white noise generation module

In this paper, we need to produce band limited white Gaussian noise. Because pseudo-random noise has some statistical characteristics similar to random noise and has the characteristics of random noise, we use register sequence similar to code generator to generate pseudo-random m sequence. Because the noise characteristic of m-sequence is related to its period length, the longer the period, the closer to the white noise spectrum. If the symbol period of m sequence is, then it can be considered as having uniform power spectrum in the range of 0 ~ 0.45 / (Hz). Therefore, the simulated white Gaussian noise in the desired frequency range can be obtained by controlling.

4. Hardware implementation and operation results

The design scheme of the GPS digital IF signal source is completed in the Simulink environment, and the FPGA hardware description file and hardware test file are generated by system generator tool, and compiled and synthesized in Xilinx ISE environment. At the same time, the hardware simulation is carried out with Modelsim. Finally, the bit stream file generated by Xilinx ISE is downloaded to the FPGA hardware platform using Xilinx xc2s200 chip for hardware system implementation and signal verification. Figure 3 shows the time domain waveform and power spectrum of GPS digital IF signal generated by the simulation signal source designed based on this scheme (satellite PRN is 1, if frequency is 15.42mhz, SNR is 10dB). Through the comparison with the actual GPS IF signal and its power spectrum, it is found that the two characteristics are consistent.

Figure 3 GPS digital IF signal and power spectrum generated by simulation signal source

5. Conclusion

Based on the mathematical model of GPS digital IF signal source, this paper proposes a design scheme of GPS digital IF signal source, which has the flexibility of software design and real-time efficiency of hardware design, based on the shortcomings of pure hardware and software design. The scheme realizes the simulation of multiple visible satellite signals through multi-channel parallel structure, realizes the generation and synchronization of C / a code and P code corresponding to any GPS time through code generator and setter, and simulates the multipath effect and noise environment in the process of signal transmission through multipath and Gaussian white noise module. The selection of satellite PRN and the key parameters of each module are calculated, set and managed in a centralized way, which facilitates the parameter adjustment, the research on the effects of various effects and the cooperation with other signal processing modules. The integrated process based on system generator is adopted in this design, which not only reduces the workload of hardware design due to system modification and upgrading, but also makes up for the shortage of real-time performance of software scheme. It also provides a new idea for the design of other modules of GPS receiver and other signal processing systems. The design and implementation of this signal source is an important part of the independent development of GPS and other satellite navigation system receivers. It can produce considerable social and economic benefits in the process of civil industrialization of satellite navigation system.

The author’s innovation point: This paper puts forward an efficient integrated FPGA design scheme of GPS digital IF signal source, which has both software design flexibility and hardware design real-time efficiency.

Editor in charge: GT


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