With the rapid development of semiconductor manufacturing technology and multimedia technology, image sensor, as the core component of image acquisition equipment such as digital camera and camera, is becoming the focus of current and future research. According to the type, the image sensor can be divided into CCD type and CMOS type. CCD (charged coupled device) technology was first proposed by Bell Laboratories in 1969 and has a history of 25 years. It uses a special VLSI process to generate a tightly compressed multi silicon electrode grid on the silicon wafer surface to collect charges through photoelectric efficiency. In the past 20 years, CCD image sensor has occupied the image sensor market with its advantages of high sensitivity, low noise and wide dynamic range. However, with the expansion of the application scope of CCD, its shortcomings are gradually revealed. Firstly, the CCD photosensitive unit array is difficult to be monolithic integrated with the driving circuit and signal processing circuit, and it is difficult to process some analog and digital functions, including the functions of analog-to-digital converter, precision amplifier, memory, operation unit and other components. Secondly, the pulse driven by CCD array is complex, Relatively high operating voltage is required, which is not compatible with deep submicron VLSI technology, and the disadvantage of high power consumption of CCD seriously limits its application in portable electronic devices. The concept of MOS image sensor first appeared in the 1960s, but it was not studied at that time due to the limitation of large-scale integrated circuit technology. With the development of VLSI and micro machining technology, recently, people have successfully integrated image sensor, analog-to-digital conversion circuit, image processing circuit and other modules into a CMOS image sensor chip, so as to achieve low power consumption, high performance, high integration and high reliability, and greatly reduce the system cost and area, CMOS image sensor began to break through the shortcomings of poor imaging quality, and gradually became a research hotspot in the field of image sensor.
2. Classification of integrated a / D converter
Any a / D converter has the basic functions of sampling, quantization and coding. Sampling discretizes the analog signal in time and turns it into a sampling signal; Quantization is to discretize the amplitude of the sampled signal into a digital signal; Coding is the final representation of digital signal into a form acceptable to digital system. How to realize these three basic functions determines the structure and function of a / D converter. According to the signal processing methods, a / D converters can be divided into parallel processing a / D converters and serial processing a / D converters. The parallel structure has fast processing speed and complex structure, and the serial A / D converter has simple structure and slow processing speed. According to different quantization and coding methods, it can be divided into PCM type A / D converter with Nyquist frequency sampling and uniform quantization and oversampling type A / D converter with incremental modulation.
According to different integration methods, the A / D converters used in CMOS image sensors can be divided into three main types: chip level integration, column level integration and pixel level integration.
2.1 chip level integration
Chip level integration is that the whole sensor array uses a high-speed A / D converter. The advantage of this structure is that because the A / D converter is placed outside the sensor array as an independent unit, the area of the A / D converter is not strongly limited. The disadvantage is that the high conversion rate of a / D converter will bring large power consumption, and because the data transmission between sensor array and a / D converter unit is analog signal, it will inevitably introduce additional noise and affect the performance of the whole system.
2.1.1 parallel structure a / D converter
Parallel structure a / D converter is mainly composed of resistance voltage divider, comparator and encoder. Its working principle is that each stage needs a comparator and a voltage dividing resistance, and the reference voltage of the comparator is generated through the series resistance. The comparator outputs the comparison result between the input signal and the reference voltage to a decoder and outputs the digital quantity after decoding. The main advantage of this structure is that the sampling speed is only limited by the speed of the comparator, so the sampling speed is fast. It is the highest A / D converter at present. The main disadvantage is that a large number of comparators are used, and the number of comparators increases exponentially relative to the sampling accuracy, so the chip area increases sharply, and the accuracy integrated in the CMOS image sensor chip is about 8 bits. In 1998, loinaz, an American scholar, successfully integrated an 8-bit parallel a / D converter into the image sensor chip. It works at 3.3V voltage and the power consumption is 200MW.
In order to overcome the problems of too many comparators and too large area caused by parallel structure, a semi parallel structure a / D converter is proposed. The semi parallel structure is reconstructed from high-order and low-order parallel structure a / D converters with different accuracy into an A / D converter, which is output from high-order and low-order respectively. Although the speed of semi parallel structure is half that of parallel structure, the number of comparators is also reduced to half of the original. This semi parallel a / D converter is used in the monolithic video recording chip of Smith et al.
2.1.2 pipelined A / D converter
Pipelined A / D converter is the combination of pipelined and semi parallel a / D converter. It divides the whole sampling process into several stages through the pipeline. Each stage is composed of a low-precision semi parallel a / D converter, a D / a converter and a sample and hold amplifier circuit. Each stage outputs digital quantity through one stage, and the signal subtracts the quantity of the output digital signal fed back by DAC to the next stage. In this way, 1-2 bits are sampled at each stage, and then combined for parallel output. Although the sampling speed is affected by the number of stages and needs several clock cycles to output, due to the pipeline structure, it can still achieve a fast conversion speed and effectively control the area and power consumption. In recent years, pipelined A / D converters are widely used in various high-speed data conversion circuits and CMOS image sensor chips.
2.2 column level integration
Column level integration uses semi parallel a / D converters to realize the analog-to-digital conversion of the whole image sensor by integrating an array of medium and low-speed A / D converters. Each a / D converter only completes the conversion of one or several rows of pixels. The main advantage of column level a / D converter is that simple medium and low speed A / D converter can be used. The disadvantage is that it will make the chip layout more complex.
2.2.1 successive approximation A / D converter
Successive approximation A / D converter can provide 8-bit to 18 Bit analog-to-digital conversion with the fastest speed of about 5msps. It uses a comparator, a sample and hold circuit, an n-bit DAC, an n-bit shift register and a SAR logic. This structure uses the method of data successive approximation through the loop to achieve the required accuracy. To achieve n-bit accuracy, you need to cycle and compare N cycles. The disadvantage of this recycling structure is that the sampling speed of a / D converter is slow. The advantage is that the chip area is small. Another characteristic of this type of a / D converter is that the power consumption of the circuit increases in proportion to the sampling rate, unlike the fixed power consumption of the corresponding sampling rate of fully parallel and pipelined A / D converters. The successive comparison a / D converter has been successfully integrated at the column level in the image sensor chip of R. panicacci, and has achieved good application results.
2.2.2 unilateral integral A / D converter
Unilateral integral A / D converter can provide high-precision analog-to-digital conversion and has good noise suppression. The working principle of single-sided A / D converter is that an unknown input circuit voltage Vin is integrated through RC circuit. The integration result VINT is compared with the known reference voltage Vref. It is known that the integrated voltage VINT is proportional to the input VIN voltage and the integration time t, that is, VINT / Vin is proportional to the achieved integration time. Therefore, the size of VIN can be determined according to the time taken for tint to be equal to VREF.
The limiting factors of this structure a / D converter are the accuracy of and the accuracy of RC. Therefore, the small transformation of reference voltage, resistance and capacitance will affect the conversion accuracy. The single-sided integral A / D converter is successfully integrated with the chip.
2.2.3 periodic A / D converter
Periodic A / D converter is similar to pipelined A / D converter in principle. It is structurally equivalent to the first order of pipelined A / D converter, and achieves the required accuracy through multi cycle calls. The working principle is that when the read control signal rises, the input signal is read into the circuit, then sampled in the A / D converter circuit, the result is stored in the register output, and then subtracted from the original signal through a DAC. The remaining signal is amplified to the original size through the sample and hold amplifier, and the next sampling is carried out when the feedback control signal rises. This periodic reuse structure reduces the power consumption and provides the conversion from medium and low speed analog signal to digital signal. In 1998, Professor S. Decker  published at the ISSCC conference that the A / D converter with this structure adopts 0.8 process and 5V voltage for 256 × 256 pixel image sensor chip.
2.2.3 pixel level integration
The characteristic of pixel level integration is that each photodetector or several photodetectors share a low-speed A / D converter, and a large number of low-speed A / D converters work in parallel to achieve the effect of a high-speed A / D converter. The pixel level a / D converter changes the communication between the center and the surrounding of the image sensor from analog signal to digital signal, which reduces the signal loss in the original analog signal transmission process. The integration of pixel level a / D converter and pixel sensor brings the repeatability of image sensor structure, so that there are many repeating units in the image sensor, so it has scalability. Although the pixel level a / D converter has many advantages, the pixel level a / D converter is integrated in the pixel unit, the area of the A / D converter is limited by the fill factor, and the number of a / D converters and the number of sensor pixel units are in the same order of magnitude, so the pixel level a / D converter has very strict requirements on power consumption and area, Therefore, the traditional A / D converter structure is difficult to be integrated with the image sensor as a pixel level a / D converter.
Fig. 6 is a schematic diagram of a readout circuit using a pixel level a / D converter, which is composed of n × M pixel cell array, row decoder, high-precision amplifier and column address decoding / output checker. One a / D converter and a plurality of photodetectors form a pixel unit.
At present, the A / D converters used in pixel level mainly include oversampling sigma delta structure a / D converter proposed by Fowler and multi – channel – bit – serial (MCBS) structure a / D converter proposed by Yang.
2.3.1 simplified oversampling sigma delta structure a / D converter
Oversampling sigma delta A / D converter is characterized by less proportion of analog part and low accuracy requirements (reducing the impact of VDD fluctuation, device matching and kt / C noise on circuit performance), and large proportion of digital part, which is more suitable to be realized by standard CMOS process. The first-order oversampling sigma delta has the advantages of simple structure, low speed and high precision, which just meets the requirements of pixel a / D converter of image sensor. The principle of a / D converter with first-order oversampling sigma delta structure is shown in Figure 7.
After oversampling, the input signal is integrated by the integrator, and then fed back to the input through the quantizer. At the same time, the quantized digital signal is output. The digital signal is reduced to Nyquist frequency through comb filter.
Fowler uses the idea of sigma delta A / D converter to improve the traditional sigma delta A / D converter and simplify the circuit. A simplified sigma delta A / D converter circuit with CMOS pixel level integration is proposed.
One unit uses four photodetectors and a pixel level a / D converter, which is realized by 17 tubes. During operation, since the photodiode after sensitization generates light charge, the light charge is stored in the photodiode section capacitor to generate node voltage, the converter selects a photodiode through the checked device, and the section voltage of the selected photodiode is quantified through the clock controlled comparator.
In this design, the comparator operates in the sub threshold region to reduce power consumption and noise, increase gain, and reduce the leakage current in the D / a converter. The bias current is also set to be small enough to complete the required sampling rate,. This one bit D / a converter is realized by an analog signal shift register.
Because the digital part is complex and occupies a large area, Fowler only integrates the analog part of sigma delta A / D converter with the image sensor chip, and puts the digital part out of the chip. This method reduces the chip area, but oversampling will lead to a huge amount of output data. Because the digital part is set outside the chip, it requires high I / O bandwidth for large-size or high-speed CMOS image sensor chip, so its application range is limited.
2.3.2 MCBS structure a / D converter
The traditional bit parallel and bit serial A / D conversion technology can not be used as pixel level integrated a / D converter due to the limitations of area and power consumption. In 1998, David Yang, a scholar at Stanford University, proposed the first pixel level a / D converter with Nyquist rate MCBS (multi channel bit serial) structure. Its sampling frequency is only twice the signal frequency, so there will be no problem of too much signal output data. It is composed of pixel unit circuit and chip level circuit. Each pixel unit is composed of a comparator and a latch. All pixel units share a finite state machine circuit and an m-bit DAC circuit.
The conversion principle is to find out the rules of each bit by studying the coding table. Taking a 3-bit gray code for an input signal between 0 and 1 as an example, to judge the MSB bit, only compare the input signal with 1 / 2, and to judge the LSB bit, compare the signal with 1 / 8, 3 / 8, 5 / 8 and 7 / 8. This comparison is implemented in parallel architecture a / D by simultaneous comparison. Here we realize the serial comparison of you through multiple clocks.
Through the serial multi bit comparison of a step rising ramp signal provided by the finite state machine and the input analog signal through multiple clock cycles, the 3-bit precision A / D converter needs one clock cycle to calculate the highest bit, two clock cycles to calculate the secondary high bit and four clock cycles to calculate the lowest bit, The results are sent to the latch controlled by the bitx signal provided by the finite state machine and output serially. The MCBS structure a / D converter simulates the parallel comparison between the resistance voltage division in the full parallel a / D converter and the multiple bits of the input analog signal through the multi cycle multiplexing technology, which greatly reduces the area of the A / D converter and can be realized by a stable and simple circuit.
Yang’s mcsb A / D converter uses 18 transistors.
With the development of SoC technology, the advantages of CMOS image sensor in high integration are more and more reflected, and the integrated a / D converter is the core component of CMOS image sensor. Scientific researchers all over the world have started the research work in this field for a long time. Stanford University in the United States began its research in this field as early as the early 1990s, and has achieved fruitful results in pixel level a / D converter. Although the Institute of microelectronics of the Chinese Academy of Sciences started relatively late, through unremitting efforts, we have made some research achievements in column level and chip level a / D converters. At present, there are several research directions in this field.
3.1 low voltage
Integrated circuit design has entered the era of deep submicron. The minimum linewidth has changed from 0.25 to 0.18 to 0.13. The power supply voltage has also decreased to 2.5V, 1.3V, or even below 1V, which has brought great help to the design of digital circuits. Low voltage means low power consumption, but it is a great challenge for analog circuit design. How to keep the A / D converter working normally under low voltage and improve the dynamic range and signal-to-noise ratio of analog signal has become a hot issue in the future.
3.2 low power consumption
The image sensor chip mainly used in portable devices has particularly strict requirements on the power consumption of the chip. The power consumption of pixel level and column level integrated a / D converter will greatly affect the power consumption of the whole chip. Therefore, how to better control the power consumption of a / D converter and reduce the power consumption of the whole system, so as to prolong the battery life of portable video system, is one of the main problems that analog IC designers need to consider.
3.3 improve conversion accuracy and speed
The proposal of new generation video technology and 3D video technology has higher requirements for video picture quality, and the conversion accuracy and speed of a / D converter are the key factors affecting video picture quality. The number of frames of video playback is limited by the conversion speed, and the image quality of video is affected by the conversion accuracy. How to develop a high-speed and high-precision A / D converter for image sensor to meet the growing requirements of high-quality digital video has also become an urgent problem to be solved.
Responsible editor: GT