Table of contents:

  • 1. DDR3 pin definition
  • 2. Startup process
  • 3. Rough classification of signal groups
  • 4. Wiring rules
  • 5. The spacing between CPU and DDR, DDR and DDR
  • 6. Routing method: point-to-point, T-type topology, daisy chain topology
  • 7. Notes

1. DDR3 pin definition

CK/CK# Global differential clock, all control and address input signals are sampled at the intersection of the rising edge of CK and the falling edge of CK#, and the output data strobe (DQS, DQS#) is referenced to the intersection of CK and CK#.

CKE is a clock enable signal that enables (high) and disables (low) the clocks on internal circuits and DRAM. Certain circuits are enabled and disabled depending on the DDR3 SDRAM configuration and operating mode. When CKE is low, it provides precharge and self-refresh operation (all banks are idle), or active power-down (row active in any bank). CKE is synchronized with power-down state entry, exit, and self-refresh entry. CKE exits asynchronously with self-refresh, and the input buffers (except CKE, CK#, RESET#, and ODT) are disabled during power-down. Input Buffers (except CKE and RESET#) are disabled during self-refresh. CKE reference value VREFCA.

CS# is the chip selection signal, enabling (low) and prohibiting (high) command decoding, most of CS# is high, all commands are shielded, CS# provides the Bank selection function of the multi-Bank system, CS# is the command Part of the code, the reference value of CS# is VREFCA.

ODT on-chip termination enable. ODT enables (high) and disables (low) on-chip termination resistors. When enabled for normal operation, ODT is only valid for the following pins: DQ[7:0], DQS, DQS#, and DM. If disabled by the LOAD MODE command, the OTD input is ignored. The reference value for OTD is VREFCA.

BA0, BA1, BA2 are BANK address inputs, which are used to determine which BANK the current command operation is valid for. BA[2:0] defines which mode (MR0, MR1, MR2) of the device is loaded in the LOAD MODE command, and the reference value of BA[2:0] is VREFCA.

A0~A9, A10/AP, A11, A12/BC#, and A13 are address buses, which provide row addresses for valid commands, and provide column addresses and automatic precharge bits (A10) for read and write commands, so as to read from a Bank Select a location in the memory array of the LOAD MODE commands the device, and the address input provides an opcode. The reference value for address input is VRECA. A12/BC# is when the mode register (MR) is enabled, A12 is sampled during read and write commands, and it has been determined whether burst chop (on-the-fly) is executed (HIGH=BL8 executes burst chop) or LOW-BC4 Burst chop is not performed.

RAS#, CAS#, WE# are row selection, column selection and write enable signals respectively, active low. These three signals together with CS# form the command signal of DDR.

DM is a data mask (shielding) signal. When writing data, when the DM signal accompanying the input data is sampled high, the input data is masked. Of course DM is only used as an input pin, however, the DM load is designed to match the load of the DQ and DQS pins. The reference value for DM is VREFCA. DM is optional as TDQS.

DQ0~DQ7 are data buses, and data signals during read and write operations are input or output through the bus.

RESET# is a reset signal, low effective, and the reference value is VSS.

DQS and DQS# are data strobe (latch) signals, both edges are valid, input when writing data, the signal edge is aligned with the data center, output when reading data, and the signal edge is aligned with the data edge.

TDQS, TDQS# output signal, terminal data strobe, when TDQS is enabled, DM is prohibited, TDQS and TDDS provide terminal resistance.

VDD power supply voltage 1.5V±0.075V.

VEDO is DQ power supply 1.5V±0.075V. To reduce noise, isolation is done on chip.

VREFCA is the reference voltage for control, command and address. VREFCA must maintain the specified voltage at all times (including self-refresh).

VREFDQ is the reference voltage for data. VREFDQ must maintain a specified voltage at all times (except self-refresh).

VSS is ground.

VSSQ is the DQ ground, and in order to reduce noise, it is isolated on the chip.

The ZQ output drives the external reference for calibration, this pin should be connected with a 240 ohm resistor to VSSQ.

2. Startup process

First, the chip enters power-on, and after power-on is at least 200us to a stable level, wait for 500us for CKE to be enabled. During this period, the chip starts to initialize the internal state, and this process has nothing to do with the external clock. Before the clock enable signal (cke), it must be kept for a minimum of 10ns or 5 clock cycles. In addition, a NOP command or a Deselect command is required to appear in front of CKE. Then DDR3 starts the process of ODT. Before reset and CKE are valid, ODT is always high impedance. After CKE is high, wait for tXPR (minimum reset CKE time), and then start reading the mode register from MRS. Then load the registers of MR2 and MR3 to configure the application settings; then enable the DLL and reset the DLL. Then start the ZQCL command to start the ZQ calibration process. After waiting for the calibration to end, DDR3 enters a state where it can operate normally. For the basic configuration process, that’s it for now.

3. Rough classification of signal groups

Address line, clock differential, command control line, there are many signals in this group, and the wiring does not necessarily have to be on the same layer

8 data high bits, 1 data mask, 1 pair of data latch differential, a total of 11 lines, the same group of signal lines go on the same layer.

8 data low bits, 1 data mask, 1 pair of data latch differential, a total of 11 lines, the same group of signal lines go on the same layer.

Remarks: Signals of the same group must go on the same floor, and signals of different groups can go on different floors.

power and ground

4. Wiring rules

Try not to route the signal lines on the top or bottom layer, drill holes near the pads, and route to the middle layer. The transmission rate of the top or bottom signal wires is slower than that of the middle layer. The top and bottom layers are not routed, which is convenient for placing components.

The drilled holes should be aligned as much as possible, which is beautiful and more conducive to thread pulling.

In the same group of signals, the differential line is preferentially pulled through, and at the same time, more space is reserved for the differential line pair in advance to facilitate subsequent equal lengths.

The wiring meets the 3W principle, such as the line width W = 0.1mm, the distance between the center of the line and the line is 3W = 0.3mm, and the distance between the line and the edge of the line is 2W = 0.2mm. Prevent crosstalk between signals.

Single ended 50 ohm, differential 100 ohm.

Complete reference plane.

Do not have other signals interspersed into the DDR routing area.

The VREF power line should be as wide as possible >=20~30mil.

The differential pair error should be controlled within 5mil as much as possible.

The error of the data line should be controlled within +/-20mil as much as possible

The address line error should be controlled within +/-50mil as much as possible

5. The spacing between CPU and DDR, DDR and DDR

When a CPU is only connected to one DDR, the spacing is about 900~1000mil. If there is a series resistance in the middle, the range is 1000~1300mil.

Note: This distance is not the distance from the center of the CPU to the center of the DDR, but from the center of an approximate area of ​​the pad related to the CPU to the DDR to the center of the DDR.

When a CPU is paired with two DDRs, the two DDRs must be placed strictly symmetrically relative to the CPU (also symmetrically relative to the O point).

6. Routing method: point-to-point, T-type topology, daisy chain topology

Point-to-point, one CPU is only connected to one DDR, and only point-to-point wiring can be used.

T type: One CPU pairs two DDRs or four DDRs, the line goes from point A to point B, and point B branches to points C and D respectively.

Daisy chain, one CPU to two DDRs or 4 DDRs, the line in the figure below is from point A to point B, point B to point C.

7. Notes

The model integrity of the daisy chain method is relatively better, and most of the big brands generally use the daisy chain.

To quickly identify which method is used, you can directly view the address line group.

When there are two DDRs, how to determine whether to use a T-type or a daisy chain mainly depends on the position of the address line pad of the CPU.

If the pad of the address line is at the edge of the CPU BGA, you can consider using a daisy chain, and if it is near the middle, consider T-type.

If the pad of the address line is close to the middle of the edge, the T-type method can be considered.

It is easiest to distinguish DDR1/2/3, mainly depending on the power supply voltage.

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