DDR2 circuit design
In the application of high-speed big data, high-speed and large-capacity cache is an essential hardware. Currently, the widely used high-speed and large-capacity memories in FPGA systems include low-speed SDRAM memory with a single data rate, and high-speed double-rate DDR, DDR2, and DDR3 SDRAM memories. DDR series of memories all require FPGA chips. There is corresponding hardware circuit structure support. For Altera Cyclone IV series FPGAs, it supports up to DDR2 memory (DDR3 memory is not supported, and Cyclone V series FPGAs only support DDR3 memory). Core Airline AC6102 development board is a high-speed application development board. In order to ensure the storage bandwidth and capacity of the system, a set of 32-bit DDR2 memory is designed on the circuit. The interface clock rate can reach 200MHz, and the equivalent data rate is 400MHz. The overall system The bandwidth is 32bit*400M = 12.8Gb/s.
DDR2 and FPGA connection method
The capacity of each DDR2 memory is 1Gb, and two DDR2 chips are combined to obtain a total capacity of 2Gb. The single DDR2 memory is 16bit, the two pieces of memory share the control line and the address line, and the data lines are parallel, that is, a 32-bit 2Gb memory module is formed.
As shown below:
CS, WE, CAS, RAS, CLK, CKE, ODT, Addr, BankAddr of two pieces of DDR2 are connected together
The 16-bit data line DQ[15:0] of DDR2_1 is connected to the FPGA as the lower 16-bit data line of the 32-bit DDR2 storage circuit, namely DDR2_DQ[15:0]
The 16-bit data line DQ[15:0] of DDR2_2 is connected to the FPGA as the upper 16-bit data line of the 32-bit DDR2 storage circuit, that is, DDR2_DQ[31:16]
The 2-bit DQS and DM of DDR2_1 are respectively connected to the FPGA as DQS[1:0] and DM[1:0] of the 32-bit DDR2 storage circuit
The 2-bit DQS and DM of DDR2_2 are respectively connected to the FPGA as DQS[3:2] and DM[3:2] of the 32-bit DDR2 storage circuit
DDR2 power supply design
The DDR2 circuit uses 1.8V power supply. In order to ensure that DDR2 can run with sufficient energy, one DCDC output of the power supply chip TPS650243 on this board is used as the 1.8V power supply of DDR2.
In addition, whether the reference power supply of DDR2 is stable also directly determines the stability of DDR2 operation. The reference power supply voltage of DDR2 is half of the working voltage, that is, 0.9V. In a general low-cost design solution, this voltage can be obtained by dividing the voltage between two resistors with the same resistance value with 1% accuracy. In order to ensure the absolute reliability of DDR2 operation on AC6102, a dedicated DDR series memory power supply chip LP2996M is selected. This power supply can obtain the output of half of the working voltage of the DDRx chip which is accurate and stable as the DDR2 reference source (VREF), and can provide DDRx A series of terminal regulated power supply (VTT), VTT is to provide power for the terminal resistance when DDR2 needs a parallel terminal resistance. Only when more than two DDR2 chips are used in parallel, the need for parallel terminal resistance is considered. This design only Two DDR2 chips are used, so the VTT output of this chip is not actually needed.
Pin assignment strategy when FPGA is connected to DDR2
As a high-speed large-capacity memory, DDR2 has an interface clock rate of up to 200M, and is in DDR mode, with an actual interface data rate of 400M. Under such a high interface speed, the pin assignment of FPGA is also quite particular. According to the relevant instructions in the Altera Cyclone IV series device manual, when the IO port is configured in single-ended mode, the device with the speed grade of C8 has the highest upper and lower banks. It can support IO rate of 167M, and the left and right banks can only support up to 133.3M. Therefore, for DDR2, the pins need to be distributed in BANK3+4 or BANK7+8. Of course, if C6 devices are used, the speed of BANK3, 4, 7, and 8 (ie, upper and lower banks) can reach 200M, while BANK1, 2, 5, and 6 (ie, left and right banks) can only reach 166.7M.
That is, the pin assignment of DDR2 needs to meet the following conditions:
I hope the speed is high, try to allocate it in BANK3+BANK4 or BANK7+BANK8
The data bus is grouped according to 8-bit or 16-bit. For this device with 256 pins, due to the limited number of pins in each bank, it is recommended that the lower 8 bits and the upper 8 bits be allocated in the same Bank respectively. At the same time, the corresponding DQS And DM should also be allocated in the corresponding BANK corresponding to the DQ data packet. For devices with 484 pins or more pins, each 16-bit data line and corresponding DQS and DM are allocated in the same BANK
The IO level of DDR2 is 1.8V, so the FPGA is connected to the bank of DDR2, and its IO power supply voltage should be 1.8V
As mentioned above, the IO level of DDR2 is 1.8V, so the IO power supply voltage page of the FPGA corresponding to the Bank should be 1.8V. On AC6102, DDR2 is connected to the BANK3 and BANK4 of the FPGA, so set the corresponding IO BANK power supply of the FPGA chip. is 1.8V, as shown in the following figure:
Through the introduction in this section, we understand the circuit principle and precautions of connecting FPGA to DDR2 chip. You can design your own software and hardware system according to your own needs and combined with the schematic diagram we provide. If you have special needs, please contact us for assistance.
Gigabit Ethernet Circuit Design
As an interconnected interface, the Ethernet interface is widely used today. From home broadband, to server data exchange, to industrial control, Ethernet can be seen everywhere. FPGA system uses Ethernet, which is mainly used for high-speed and long-distance data transmission, such as LED large-screen display, monitoring system, etc. The Ethernet data link was also transmitted from the early telephone line, to the later special twisted pair, to optical fiber, high frequency radio, and now the relatively new LIFI.
Ethernet to FPGA Connection
The AC6102 development board provides a Gigabit Ethernet interface, which consists of a Gigabit Ethernet PHY and a network transformer interface. When Ethernet data needs to be sent, the FPGA sends the data to the PHY chip. After the PHY chip encodes the data, the data is loaded onto the network cable through the network transformer. The data is delivered to the receiver via the network. The data sent from the remote end is transmitted to the network transformer through the network cable, and the output of the network transformer is connected to the PHY chip. After the PHY chip decodes the signal, the actual data is obtained, and then the data is transmitted to the FPGA chip. The functional block diagram of FPGA to realize Gigabit Ethernet data transmission is as follows:
RTL8211 is an Ethernet physical layer transceiver that supports GMII, RGMII, and MII interfaces, and can work in 100M Base or 1000M Base mode. The interface can be set to GMII, RGMII, MII interface. And several pins are provided to configure the working mode.
The AC6102 uses the GMII interface by default. The way to achieve this configuration is to connect the corresponding configuration pin E_COL (yes, this pin, the chip will detect the state of this pin when it is powered on, and determine the working mode according to the state of the pin , and it is the normal COL function when it is working normally) is connected to GND through a 10K resistor.
The Ethernet physical layer chip has a device address, which can be set through external pins. In the above figure, R20, R21, and R24 are connected to VCC or GND to determine the device address of the chip to be 001b. Of course, these states are only read when the chip is powered on. When the chip is working normally, these pins return to their normal functions.
Connect to FPGA pins
All the signals connected to the FPGA of the Ethernet circuit on the AC6102 are distributed to the BANK8 of the FPGA to obtain a more ideal timing constraint effect. The following is the connection relationship between the RTL8201 chip and the FPGA.