EnDat interface is a digital, full duplex synchronous serial data transmission protocol specially designed by Heidenhain for encoder. It has the advantages of fast transmission speed, powerful function, simple connection and strong anti-interference ability. It is a general interface for data transmission of encoder and grating ruler. This paper expounds the characteristics, functions, timing, data transmission and OEM data storage of EnDat interface, and introduces the subsequent circuit design scheme of encoder data acquisition and the principle and principle of FPGA module design.

I. overview

The absolute encoder uses natural binary, cyclic binary (gray code) or PRC code to photoelectrically convert the physical marking on the code disk, and converts the rotation angle of the connecting shaft into the corresponding electric pulse sequence and outputs it in digital quantity. It has the advantages of small volume, high precision, digital interface and absolute positioning. It is widely used in many fields, such as radar, turntable, robot, CNC machine tool and high-precision servo system. The data output of absolute encoder is mainly synchronous serial output. EnDat interface is a digital and full duplex synchronous serial interface specially designed by heidenham for encoder. It can not only transmit position values for incremental and absolute encoders, but also transmit or update the information stored in the encoder or save new information. Due to the use of serial transmission mode, only four signal lines are needed. Under the clock excitation of subsequent electronic equipment, the data information is transmitted synchronously. The data type (position value, parameter, diagnostic information, etc.) is determined by the mode command sent by the subsequent electronic equipment to the encoder.

II. Introduction to EnDat interface

1. Features of EnDat interface

★ high performance and low cost: the universal interface is applicable to all incremental and absolute encoders, with more economical power consumption, small size and compact connection mode, fast system configuration, and zero point can float according to the offset value.

★ better signal quality: special optimization inside the encoder improves the system accuracy and provides better contour accuracy for the NC system.

★ better practicability: automatic system configuration function; Digital signal improves the reliability of the system; Monitoring and diagnosis information is conducive to the safety of the system; Redundancy code verification is conducive to reliable signal transmission.

★ improve the security of the system: two independent position information and error information bits, data checksum and response.

★ applicable to advanced technology development: (high resolution, short control cycle, fastest 16m clock, safety design concept) applicable to direct drive technology.

Data acquisition design of EnDat interface encoder based on FPGA

Fig. 1 data acquisition schematic diagram of EnDat interface encoder

2.EnDat2. 2. Improvement of encoder performance

★ the transmission position value and additional information can be transmitted at the same time: the type of additional information can be selected through the storage address selection code.

★ the encoder data storage area includes encoder manufacturer parameters, OEM manufacturer parameters, operation parameters and operation status, which is convenient for the system to realize parameter configuration.

★EnDat2. 2 encoder realizes all digital transmission, and the processing of incremental signal is completed inside the encoder (built-in 14bit subdivision), which improves the quality and reliability of signal transmission and can achieve higher resolution.

★ monitoring and diagnosis function. Alarm conditions include: failure of light source, insufficient signal amplitude, wrong position calculation, too low or too high operating voltage, too large current consumption, etc; A warning signal is provided when some limit values of the encoder are approached or exceeded.

★ wider voltage range (3.6 ~ 14V) and transmission rate (16m).

3. Timing and OEM data storage

During synchronous data transmission of each frame, a data packet is sent, and the transmission cycle starts from the first falling edge of the clock. The measured value is saved and the position value is calculated. After two clock pulses (2t), the subsequent electronic equipment sends the mode command “encoder transmits position value” (with or without additional information).

After calculating the absolute position value (tcal – see Figure 2), the encoder transmits data to the subsequent electronic equipment from the start bit. The subsequent error bits F1 and F2 (only exist in endat2.2 instruction) are group signals serving all monitoring functions and fault monitoring. Their generation is independent of each other, which is used to represent the encoder fault that may lead to incorrect position information. The exact cause of the fault is stored in the “running state” storage area and can be queried by subsequent electronic equipment.

From the lowest bit, the absolute position value is transmitted, and the length of the data is determined by the type of encoder used. The number of clock pulses required to transmit the position value is saved in the parameters of the encoder manufacturer. The transmission of position value data ends with cyclic redundancy detection code.

Data acquisition design of EnDat interface encoder based on FPGA

Figure 2 location value transmission without additional information

If the location value has additional information, the additional information 1 and 2 are immediately followed by the location value, and they also end with a CRC. The content of the additional information is determined by the selected address of the storage area, and then transmitted in the subsequent sampling period. This information is transmitted in subsequent transmissions until a new storage area is selected. At the end of the data word, the clock signal must be set high. After 10us to 30us or 1.25us to 3.75us (endat2.2 programmable recovery time TM), the data line returns to the low level, and then the new data transmission can start under the new clock signal.

Data acquisition design of EnDat interface encoder based on FPGA

Figure 3 location transmission with accessory information

At the same time, the encoder provides different storage areas for parameters, which can be read by subsequent electronic devices, and these areas can be written by encoder manufacturers, OEM manufacturers and even end users. Some specific areas can be write protected. Different series of encoders support different OEM storage areas and different address ranges. Therefore, each encoder must read the allocation information of OEM storage area. For this reason, subsequent electronic circuits should be programmed based on relative addresses rather than absolute addresses.

Circuit design scheme of subsequent electronic equipment with three EnDat interfaces

Users can design their own interface circuit for data acquisition and processing according to EnDat interface protocol and electrical characteristics of the circuit. At the same time, heidehan also provides specific data processing chips for users to choose. If the user designs the circuit by himself, it is necessary to follow the electrical characteristics of the EnDat interface and master the protocol of the EnDat interface to ensure that the timing requirements and data frame format of the protocol are strictly followed. If the data processing chip provided by heidehan is used, the design can be simplified. Users only need to configure the register of FPGA and send instructions according to the instruction format acceptable to the chip to obtain the required data.

Through the transceiver following RS-485 (differential signal) standard, under the excitation of the synchronous clock sent by the subsequent electronic equipment, the data (position value and parameters) can be transmitted Bi directionally between the encoder and the subsequent electronic equipment.

IV. FPGA + software macro

The partner of heidenham, Mazet company, provides software macros of EnDat protocol for virtex and Spartan series of Xilinx company and ACEX and cyclone series of Altera company. According to customer needs, Mazet company can also provide customized soft cores. The soft core realizes all the functions of EnDat interface. Users can transmit 8-bit or 16 bit data with microcontroller through 6-bit address line and 16 bit data line. The following is the module diagram and circuit design of FPGA.

Data acquisition design of EnDat interface encoder based on FPGA

Figure 4 FPGA module diagram

Data acquisition design of EnDat interface encoder based on FPGA

Fig. 5 encoder and subsequent circuit connection module diagram

Now, it has been widely used in many industries. Bidirectional endat2 The clock frequency of 2 interface has been increased to 16mhz, which can meet the application with high dynamic performance requirements such as direct drive, especially in the electronic industry. Increasing the clock frequency from 8MHz to 16mhz will not only greatly shorten the time required to read the location information, but also greatly shorten the cycle of the control loop. At the same time, the simple and economical system design provides customers with convenience, powerful function, universality and forward-looking security design concept, which guides the continuous development of coding control technology

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