This series has highlighted continuous time Σ-Δ (CTSD) architecture characteristics of analog-to-digital converter (ADC) modulator loop. This architecture can simplify the signal chain design of ADC analog input. A simple but innovative method of interfacing ADC data with an external digital host to perform application related processing on this data is now discussed. For any application, the sampling rate of digital data output is a key parameter of ADC signal chain. However, different applications have different sampling rate requirements. This paper introduces a new on-chip sampling rate conversion technology, which is used in the output of the core ADC, allowing the signal chain designer to process the ADC digital output data at the required sampling rate.

The function of ADC is to sample the analog input signal and convert it into an equivalent digital format. The sampling rate required by the application to further process the digital data is not necessarily the same as that of the ADC to sample the analog signal. Each application has unique digital output sampling rate requirements. The sampling rate converter maps the input sampling rate of ADC data to the required output sampling rate. Firstly, this paper summarizes the sampling rate requirements of various applications, and proves that ADC needs to support a wide range of output sampling rates. Then, this paper quickly reviews the traditional sampling rate conversion technology and its shortcomings in the known ADC architecture. Next, this paper introduces a novel asynchronous sampling rate conversion (ASRC), which can be paired with any ADC architecture to obtain any required output sampling rate, and simplifies the digital interface design with an external digital host.

The combination of ASRC and CTSD ADC has the best of both worlds. It can not only simplify the signal chain design of ADC analog input, but also simplify the signal chain design of digital output.

Sampling rate requirements

One of the main performance parameters of driving digital data sampling rate selection ADC is the expected accuracy of ADC. The more samples in digital data, the more accurate the representation of analog input. But the disadvantage is that it needs to process a large amount of data, and the complexity and power consumption of external digital host interface design will increase. Therefore, each application determines the sampling rate of digital data according to the required accuracy, power budget, design complexity and planned algorithm processing. Most of the general sampling rates required can be classified as follows:

Nyquist sampling rate

The well-known Nyquist sampling 1 criterion states that in order to provide a faithful digital representation of analog input, the sampling rate should be at least twice the input bandwidth. Therefore, the Nyquist sampling rate applies a digital sampling rate that is twice the target input bandwidth. A well-known example of this sampling rate is the digital audio data storage on CD. Its rate is 44.1 ksps, while the target input audio bandwidth is up to 20 kHz, which is the upper frequency limit of human hearing.

Oversampling rate

A few applications, such as frequency harmonic analysis or time domain analysis, require a sampling rate many times higher than the input bandwidth. An example of oversampling rate is the time domain analysis of transient signals in the impact detection environment, as shown in Figure 1. If the sampling rate of this signal is Nyquist sampling rate, we will not be able to understand the whole picture of the signal. With more sampling points, the signal can be reconstructed and analyzed more faithfully.

Figure 1 Time domain analysis of transient signals: (a) Nyquist sampling rate, (b) oversampling rate

Variable sampling rate

Some applications, such as coherent sampling, require adjusting the output sampling rate according to the analog input frequency with good resolution. Power line monitoring is an example of this application. Coherent sampling is required to meet the class a power quality measurement requirements specified in IEC 61000-4-30. The accuracy requirements of these standards determine that the sampling rate needs to track the frequency drift of the input line. In these applications, the clock frequency synthesizer circuit on the power line generates the output digital data sampling clock of the ADC, as shown in Figure 2.

Figure 2 Variable sampling rate: power line quality monitoring

Multi sampling rate

In multi-channel applications that detect and analyze a wide range of different types of analog inputs, such as oscilloscope or data acquisition applications, the sampling rate of each channel may be different. In this case, the ADC used in the platform should be able to flexibly support multiple sampling rates.

Figure 3 Multi sampling rate application

Therefore, the requirements of digital data sampling rate vary from application to application, and there is no universal sampling rate. Therefore, ADC facing a broad market needs to support a wide range of programmable digital data sampling rates.

Figure 4 shows a generalized ADC digital data interface with an external digital host. It should be noted that the digital data interface discussed in this paper does not include device configuration control interface, such as SPI or I2C.

Figure 4 Generalized ADC digital data interface

The core ADC uses the sampling clock with the rate of fsin to sample the analog input, as shown in Figure 4. In most data manuals, the input sampling clock itself is generally expressed as MCLK. The sampling rate of the final digital output data is fodr. Typically, these pins are labeled as ODR, drdy, or convst clocks in the data book. This paper uses the general term ODR clock to represent the digital output data clock.

The sampling rate fsin of the ADC core depends on the ADC architecture. The digital output data rate fodr depends on the data interface requirements of the external digital host. In most ADC signal chain applications, fsin and fodr can have different values and are not related. Therefore, it is necessary to convert the sampling rate and map the fsin data of ADC core to the digital output data of fodr. The following section will discuss the traditional sampling rate conversion techniques used in well-known ADC architectures, such as Nyquist ADC and oversampling ADC. In addition, we will have an in-depth understanding of other relevant digital data interface requirements.

Sampling rate conversion in Nyquist rate ADC

In Nyquist rate converter, the sampling frequency of ADC core is twice that of analog input bandwidth fin. The most common example under this category is Nyquist rate SAR ADC, whose input and output sampling rates are the same. Therefore, the digital output data rate clock ODR can be multiplexed into the ADC core sampling clock MCLK. In the SAR ADC data manual, the digital output data clock is represented as convst or drdy. However, as mentioned earlier, all these clocks are collectively referred to as ODR clocks in this paper. The combination of ODR and MCLK can simplify the digital data interface. As shown in Figure 5, only one clock wiring is required. Since the clock is provided and controlled by an external clock source or an external digital host, the ADC provides the clock externally. This means that the ADC is running in external hosting mode.

Figure 5 Simplified digital data interface of Nyquist rate converter in managed mode

According to the application requirements and analog input bandwidth, it is easy to adjust the sampling rate fodr. By adjusting fodr, we can also adjust the sampling clock rate fsin of ADC core. Another advantage is that when the fodr is adjusted, the power consumption of the whole ADC will also be adjusted linearly. This simplified digital data interface has many other extended benefits, one of which is easy synchronization in multi-channel applications.

Easy synchronization

In a single channel ADC application, the local clock provided to the ADC inherently synchronizes the digital data with the timing clock. In the application of multichannel ADC, the challenge is to ensure the synchronous sampling of multiple analog inputs and the synchronization of digital data with the edge of ODR clock for further digital processing. There are many well-known examples of multi-channel synchronization applications, such as audio applications, in which the left and right channels have specific synchronization requirements. Another typical example is the monitoring of various power lines in the power grid. Within each power line, voltage, current and power input measurements need to be synchronized. Using Nyquist rate ADC, as shown in Figure 6, multi-channel synchronization can be easily realized by sharing ODR clock and well planning its route. Well planned routing ensures that the ODR clock propagates to each ADC with the same delay and provides the best possible channel synchronization.

Figure 6 Simplify synchronization in Nyquist rate sampling rate converter

Simplified digital data interface is an important advantage of Nyquist rate converter. Some digital data interface challenges that it is not competent for are discussed below.

Limitations of Nyquist rate control

Noise adjustment

In the Nyquist rate converter based on application analog input bandwidth, the digital data clock can be easily adjusted. Clock adjustment can bring advantages in power consumption, but ADC noise will increase due to the so-called aliasing turn back phenomenon. The extension of Nyquist sampling criterion is that any information beyond Nyquist frequency will turn back or overlap back to the target frequency band. The analog input of ADC will have a lot of interference information or noise from signal source and input analog circuit, which extends to very high frequency. ADC sampling causes any input noise exceeding fsin / 2 to turn back, increasing the noise in the target input bandwidth. As shown in Fig. 7, as the sampling rate decreases, there will be more such external noise turns back, thereby increasing the noise in the ADC output.

Figure 7 Relationship between input noise turn back and sampling frequency

Clock timing constraint

For SAR ADC, the analog input sampling clock needs two stages, as shown in Figure 9A. One is the sampling stage, in which the input sampling capacitor of ADC charges the analog input; The other is the conversion phase, in which the sampled data is digitized. In order to obtain the best possible ADC performance, the sampling circuit of ADC generally has the requirement of the shortest sampling time. Therefore, the external digital host or clock source that generates this clock needs to comply with these timing constraints.

Clock Jitter

The clock routing on the application circuit board is sensitive to the power noise of the clock source or coupling with other signals on the circuit board, because the noise will increase the uncertainty of the clock edge. The uncertainty of clock edge is called jitter. There are many types of clock jitter on the sampling clock, which will affect the performance of ADC. The most common is the inter cycle root mean square jitter, which increases the variability of analog signal sampling points and leads to performance degradation, as shown in Figure 8. For more details on the impact of RMS clock jitter on ADC performance, see related article 2.

Figure 8 Clock jitter causes the uncertainty of analog input sampling points

To sum up, the increase of ADC data error caused by clock jitter can be quantified as the decrease of signal-to-noise ratio (SNR):

among σ J is root mean square jitter.

When the noise of digital host or clock source is very high, equation 1 means that in order to achieve the required SNRJ, we either limit the input bandwidth or use additional technology to filter the clock noise.

Clock jitter is a more serious challenge for multi-channel applications. Balancing the increase of jitter caused by synchronization and long clock wiring requires good clock architecture planning 3. In this case, appropriate isolation and buffering measures need to be taken to ensure that the ADC has a low-noise clock. Isolation can be achieved by using common digital isolators, but it needs to increase the budget in terms of design complexity and power consumption.

Figure 9 Limitations of Nyquist rate converter data interface: (a) clock time constraints (b) isolation requirements in multi-channel applications

After understanding the sampling rate control in Nyquist rate ADC, let’s take a look at the sampling rate control technology used in oversampling ADC.

Sampling rate conversion in oversampling ADC

As described in previous articles in this series, sampling and digitizing continuous time signals will have information loss, and quantization noise will be introduced into the sampled output. One kind of ADC follows the principle that the larger the number of samples, the higher the accuracy and the smaller the quantization noise error. Therefore, its analog input sampling rate is higher than Nyquist sampling rate, which is called oversampling. Some new precision SAR ADCs use this oversampling technology, which is called oversampling SAR ADC. Figure 10A shows the noise advantage of oversampling SAR ADC. Another type of ADC that uses the oversampling concept is Σ-Δ Type adc4, whose quantization noise QE is further shaped and pushed out to improve the performance in the target input bandwidth. Figure 10B shows Σ-Δ The noise shaping characteristics of quantization noise of type modulator. Mathematically, the sampling frequency is OSR × Fodr / 2, where OSR is the oversampling rate.

Figure 10 (a) Spectrum of oversampled SAR ADC, (b) Σ-Δ Spectrum of type ADC

If the oversampled data of the core ADC is directly interfaced with the external digital host, the latter will accept a lot of redundant information, resulting in overload. In addition, in some cases, the host may not support the strict timing constraints required for this high digital data rate transmission, and it will also lead to high power consumption. Therefore, the optimal way is to provide only the performance optimization data in the target input bandwidth. This means that the output digital data rate should be reduced or extracted to the Nyquist rate (2) × Fin), or several times the Nyquist rate, depending on the application needs. Therefore, a sampling rate converter is needed to map the high sampling rate fsin of ADC core data to the required fodr.

There is a traditional digital sampling rate conversion technology called decimation, which can filter and extract core ADC data in 2n multiples, as shown in Figure 11. An input sampling clock called MCLK is provided to the ADC. The required digital output data sampling rate (ODR / drdy) clock, which is the frequency division version of MCLK, is provided as an output. Based on the required extraction rate, the frequency division ratio is realized by setting n. For fodr programming, in order to obtain finer resolution, MCLK can also be adjusted according to the input bandwidth requirements of the application. Observe the digital data interface of oversampling ADC, and the ODR clock is given and controlled by ADC. This means that the ADC provides the clock, which is called ADC in host mode.

Figure 11 discrete time Σ-Δ (dtsd) digital data interface of ADC

Therefore, when decimation is used as a sampling rate conversion technology, ADC can provide high-performance digital data at a lower output data rate. However, this technology also has its own limitations.

Limitations of using decimation to control sampling rate

Nonlinear noise and power consumption adjustment

In variable rate applications, both or one of the extraction rate and MCLK can be adjusted. When only the decimation rate is increased, the fodr decreases and the noise decreases as the digital filter filters out more quantization noise. Only the power consumption of digital filter decreases linearly. If the MCLK is reduced as discussed in SAR ADC, the power consumption of the whole ADC will be reduced linearly, but the noise will increase due to aliasing turn back.

Many systems simultaneously adjust the MCLK and decimation rate of ADC to achieve a wide range of ODR, but this method may lead to unwanted step changes in measurement noise performance or system power consumption performance.

Clock Jitter

Because the input sampling clock frequency fsin is higher, the oversampling ADC is more sensitive to clock jitter than the Nyquist rate SAR ADC, as shown in equation 1. Therefore, the clock routing of clock source and MCLK should be planned based on the allowable jitter noise of the application. Whether single channel or multi-channel application signal chain, there will be many switching signals running on the application circuit board. The coupling from this high noise signal will increase the clock jitter on the MCLK. Therefore, in order to obtain the optimal ADC performance, we need to use digital isolator to meet the isolation requirements of MCLK. This additional design planning brings costs in terms of area and power consumption. As mentioned earlier, MCLK will also be adjusted in order to make fodr programming have finer resolution. However, the MCLK clock source with the required fsin value and jitter performance may be limited.


Realizing synchronization is another challenge of oversampling ADC. Usually, Σ-Δ One called sync is provided in type ADC_ The additional in pin is used for synchronization. SYNC_ The trigger of in pin will start the synchronous sampling of analog input and the reset of decimation filter. After the establishment time of the digital filter, the digital output data is synchronized. The digital output data during the establishment of the digital filter is interrupted, as shown in Figure 12. It also assumes that all ADCs have MCLK and sync_ The in command is synchronized. Realizing this synchronization on high sampling rate clock, especially with isolator or frequency synthesizer, will be a great challenge. A system solution dedicated to solving the challenges of data interruption and synchronization is the clock frequency synthesizer circuit, such as PLL, which generates synchronous MCLK for all channels.

Figure 12 Synchronization in dtsd ADC with data interruption

To sum up quickly, when sync is triggered_ In pin, the PLL loop starts to synchronize with the clock of the reference clock. During PLL establishment, the MCLK rate will be adjusted so that at the end of establishment, the input ADC sampling edge and ODR clock edge are synchronized. For the principle and details of this solution, see “when synchronizing critical distributed systems, the latest Σ-Δ ADC architecture can avoid data flow interruption “5.

Figure 13 Dtsd ADC synchronization solution based on PLL

The point is that compared with SAR ADC, Σ-Δ The synchronization of type a ADC or oversampled SAR ADC exceeds the requirements of on-board circuit, PLL or clock frequency synthesizer, which will increase the design complexity and power consumption. ADI has explored another novel technology, called synchronous sampling rate conversion, which can help resolve the synchronization challenge to a certain extent.

Synchronous sampling rate conversion (SRC)

For some of the challenges of simple extraction discussed, one solution is to use synchronous sampling rate conversion 6. The advantage of SRC is that the extraction rate can be any integer or decimal multiple of fsin, so fodr can be controlled more finely. ADI explored this technology and paired it with the precision dtsd converter in ad7770. For more details on SRC, please refer to the data manual or reference of ad7770.

The point is that fodr can be programmed in fine resolution in SRC, so synchronization becomes easier. For example, the extraction rate can vary in very fine steps without adjusting the external MCLK. Therefore, when sync is triggered_ When in, the channel will be synchronized, as shown in Figure 14.

Figure 14 Multi channel synchronization using SRC

Implementing finer fodr without adjusting MCLK can overcome most of the limitations of simple extraction technology. SRC also has its own limitations and challenges to overcome.

Limitations of SRC

SRC does not address the synchronization challenge of having all channels have the same MCLK.

Clock jitter / synchronization

In terms of MCLK jitter, SRC has the same limitations as simple decimation sampling rate control. The sensitivity of ADC performance to clock jitter caused by high fsin needs to be solved by the isolation gate or noise filter circuit of MCLK. In multi-channel applications, the difficulty of this challenge is further increased because MCLK has to route to multiple ADC channels. In order to achieve synchronization, MCLK and sync_ The in pin signal needs to be synchronized, as shown in Figure 16A. The challenge is that all clocks arrive at the ADC at the same time, which is related to the distance from the clock to the PCB and the possible delay caused by the barrier. A well-designed clock scheme including barrier and routing architecture needs to be established to ensure that all ADC channels experience the same delay, including isolators in the path.

Interface mode

So far, the digital data interfaces discussed are host mode and hosting mode, which are related to the core architecture of ADC. For example, the digital data clock of Nyquist rate ADC is controlled and provided by an external clock source or digital host. Therefore, they can only be set to managed mode. The oversampling ADC provides and controls the digital clock of the external digital host. Therefore, they can only be set to host mode. It can be seen that all the sampling rate control technologies discussed above have a common limitation, that is, they can not plan the data interface independently.

For most digital data interface challenges, one solution is to decouple MCLK clock domain and ODR clock domain. Therefore, ADI reintroduced a novel asynchronous sampling rate conversion technology, which makes the ODR clock and data interface clock independent of each other, thus breaking the long-standing obstacle of ADC core architecture, and the selection and control of ODR clock is no longer limited.

Asynchronous sampling rate conversion

ASRC resamples the core ADC data with fsin in the digital domain and maps it to any required output data rate. ASRC can be considered as a digital filter that can realize any non integer decimation. However, in order to achieve optimized performance, area and power consumption, decimal decimation should be processed by ASRC, and then integer decimation should be processed by a simple decimation filter, as shown in Figure 15. ASRC resamples ADC core data and takes fsin / n × Fodr extracts data. The output data rate of ASRC is n × fodr。 At the same time, the decimation filter obtains the required ÷ n decimation.

In some form of ASRC implementation, the coefficient fsin / n × The fodr can be set by the signal chain designer according to the fsin of the ADC, the required fodr and the N obtained from the decimation filter implemented on the ADC. This is similar to setting the extraction rate in SRC. The difference is that the extraction rate can be an irrational ratio and supports very fine resolution. In this case, as in SRC, the ODR clock is synchronized with MCLK and is an output generated by MCLK frequency division in the chip.

Another form of ASRC implementation is that the ODR clock is provided by an external clock source or a digital body similar to a Nyquist rate converter. In this case, ASRC has an internal clock frequency synthesizer, which calculates fsin / n × Fodr ratio and generate the required clock for ASRC and decimation filter. ODR does not need to be synchronized with MCLK and can be independently set to any sampling rate.

Figure 15 ASRC implements: (a) setting ratio, (b) on-chip calculation ratio

Therefore, no matter what form, ASRC technology supports signal chain designers to set fodr with fine granularity and break the long-standing limit, that is, fodr is limited to the integer or decimal ratio of the input sampling rate. As a result, the sampling rate and timing requirements of ODR clock now purely belong to the functional scope of digital interface, and are completely independent of the input sampling frequency of ADC. Either of these two implementation forms shows the advantages of ASRC, so the signal chain designer can simplify the design of digital data interface.

ASRC’s value proposition

Clock decoupling of MCLK and ODR

In either implementation, since fodr can be set / adjusted at a finer resolution (the adjustment amplitude can be a fraction of a Hertz), ASRC allows independent selection of MCLK and ODR clock rates. MCLK rate fsin can be selected according to ADC performance and clock jitter requirements, while ODR clock fodr can be realized according to digital data interface requirements.

Clock Jitter

In Nyquist rate converter and oversampling ADC, we all see that MCLK is related to ODR. MCLK needs to be adjusted to achieve finer resolution fodr. However, the clock source that can match the clock jitter requirements of MCLK at any fsin rate is limited. Therefore, it is necessary to weigh the ADC performance degradation caused by MCLK jitter and the possible resolution of fodr. As far as ASRC is concerned, the MCLK source can be selected to provide the best clock jitter, because the value of fsin can be selected independently, independent of ODR.

Interface mode

ASRC makes the clock rates of MCLK and ODR no longer relevant, so the selection of interface mode has a certain degree of freedom. Any ADC with an ASRC backend can be configured as a host or managed peripheral independently, regardless of the ADC core architecture.


In the previously discussed multi-channel synchronization technology, MCLK clock routing has strict requirements. Barrier and clock architectures need to be planned to meet clock jitter and synchronization requirements. Now, the MCLK source of each channel can be independent, as shown in Figure 16b. In the host operating mode, the extraction rate can be set independently to achieve synchronization. In managed mode, as shown in Figure 16b, ODRs can be shared and synchronized. Because the rate of ODR clock is low and it is only a digital data strobe clock, it does not have the strict jitter requirements like MCLK, so it can relax the strict requirements on isolation barrier or clock routing.

Figure 16 (a) Use clock and sync of SRC_ In allocation (b) simplified clock and synchronization using ASRC

In short, ASRC has opened up a way to innovate and simplify the interface with external digital hosts. In addition, MCLK can be independent, so it is very suitable for pairing with CTSD ADC.

ASRC paired with CTSD ADC

The application of CTSD ADC core to oversampling and noise shaping Σ-Δ The concept is also effective, while providing architectural advantages such as resistance input, reference drive and inherent aliasing suppression. These features greatly simplify the design of analog input front-end. As discussed in part 2, since the core ADC loop is a continuous time system, adjust the loop coefficient to the fixed input sampling rate specified in the data book.

The limitation of CTSD ADC is that MCLK cannot be adjusted as in dtsd or SAR ADC. If CTSD ADC is paired with SRC, ODR will be a function of the fixed sampling clock. This limits the scope of use of CTSD ADC. The ODR required by the application can be the irrational ratio of the fixed fsin. In addition, CTSD ADC requires the MCLK to be accurate and have low jitter to optimize ADC performance. For example, the accuracy requirement can be about ± 100ppm and the root mean square jitter is 10 PS. Therefore, MCLK will need a well planned clock architecture to ensure low jitter noise in multi-channel applications. MCLK is a high-frequency clock, so the challenge is more difficult.

ASRC can decouple MCLK and ODR, which is very suitable to deal with the limitations of CTSD ADC architecture. MCLK clock source can be local and close to ADC to avoid long clock wiring and coupling to other signals, resulting in increased jitter noise. Therefore, the combination of ASRC and CTSD ADC brings a new kind of ADC, which not only has the architectural advantages of CTSD ADC, but also can overcome the limitations of fixed and low jitter MCLK.


ASRC allows signal chain designers to independently select the required output data rate at granularity. Another advantage is that digital isolation can be effectively planned in multi-channel applications due to the decoupling of input sampling clock and ODR clock. Freely configuring the data interface without considering the core ADC architecture is another simplification of the signal chain. This paper is helpful to understand the advantages and simplification of ASRC to digital data interface compared with traditional sampling rate conversion. Generally speaking, ASRC can be paired with any ADC core architecture, but pairing with CTSD ADC can simplify the complete signal chain design of analog input terminal and digital data terminal. After clarifying the needs and value proposition of ASRC, please pay attention to the following articles. We will further elaborate the concept of ASRC and its building blocks. These details help signal chain designers understand the performance indicators related to ASRC and give full play to its advantages in application.

reference material

1Walt Kester。 “Mt-002 tutorial: what is the significance of Nyquist criterion to the design of data sampling system.” ADI, 2009.

2derek Redmayne, Eric trelewicz and Alison Smith. “Design note 1013: understand the impact of clock jitter on high-speed ADC.” Linglilt, 2006.

3Pawel Czapor。 “ Σ-Δ ADC clock – not just jitter. ” Mock dialogue, Vol. 53, No. 2, April 2019.

4Michael Clifford。 “ Σ-Δ Basic principles of type ADC topology: Part 1. ” ADI, January 2016.

5Lluis Beltran Gil。 “When synchronizing critical distributed systems, the latest Σ-Δ ADC architecture can avoid data flow interruption. ” Mock dialogue, Vol. 53, No. 3, September 2019.

6anthony O’Shaughnessy and Petre minciunescu. “An-1388: 24 bit synchronous sampling using ad7779″ Σ-Δ Type ADC realizes coherent sampling of power quality measurement. ” ADI, February 2016.

Ad1893 data book. Adi.

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