Scientific grade CCD camera is a kind of CCD camera with low noise, high sensitivity, large dynamic range and high quantum efficiency. It is used for low light level signal detection and imaging. It has been widely used in many technical fields, such as digital radiography, biomedical engineering, underwater photography, weapon equipment, astronomical observation, space earth observation and so on.
Scientific CCD camera is generally composed of high-speed CCD sensitive chip, video signal processor, timing controller, timing generator, timing driver, external optical imaging system and so on. The performance of timing generator directly determines the quality parameters of the camera. The scientific CCD camera uses the il-e2 TDI-CCD of DALSA company as the sensor. This paper analyzes the working process of il-e2 TDI-CCD chip and the requirements of driving signal. On this basis, a reasonable timing circuit is designed. In order to meet the requirements of different speed matching of image motion speed in practical work, the timing generation part is adjustable in the design of timing circuit. This design is simple, reliable and practical. After comparing the advantages and disadvantages of various hardware implementation circuits, FPGA is selected as the hardware design platform, and VHDL language is used to describe the drive circuit scheme, and EDA software is used to successfully simulate the function of the designed timing generator. Finally, the hardware circuit of xc2vp20-ff1152, a programmable logic device of Xilinx company, is adapted and debugged, and then the whole scientific CCD camera is controlled.
Working principle and driving analysis of 2 TDI-CCD
2.1 brief introduction of TDI-CCD working principle
TDI (time delay and integration) is a kind of scanning technology which can increase the sensitivity of line scan sensor. TDI-CCD is a new type of CCD with area array structure and linear array output. Compared with ordinary linear array CCD, TDI-CCD has the function of multiple series delay integration. From the point of view of its structure, multiple linear arrays are arranged in parallel, and the pixels are arranged in a rectangle in the direction of linear array and series. The diagram of pixel distribution is shown in Fig. 1.
In Fig. 1, the charge accumulation direction of TDI-CCD is along the Y direction, and the push sweep order is from the first to the 96th. In the imaging process, with the movement of the camera (or scene), TDI-CCD is sensitive from 96 to 1, and the charge is accumulated step by step from 96 to 1. Finally, the charge packet (imaging data information) accumulated by multiple delay integration is transferred to the CCD horizontal readout register and transmitted from the first stage to the operational amplifier. From the electrical characteristics of TDI-CCD, it can be seen that TDI-CCD is a single direction push broom imaging device. Compared with general CCD, TDI can increase the exposure time by means of 6,12,24,48,96 variable product grades. In the sensor imaging, because the signal storage is proportional to the exposure time, TDI-CCD can increase the photons collected by extending the exposure time. Therefore, TDI-CCD has higher sensitivity than the general linear array CCD, and can be used in low illumination environment without affecting the scanning speed. TDI-CCD can obtain high sensitivity without sacrificing spatial resolution and working speed, which makes it widely used in high-speed and low light level fields.
2.2 about DALSA il-e2 TDI-CCD image sensor
CCD image sensor is the key component of scientific CCD camera. Its performance directly affects the function and application effect of the camera. Il-e2 TDI-CCD image sensor produced by DALSA company of Canada is selected as the scientific CCD camera. The pixel structure of the TDI-CCD is 2048 × 96. A TDI-CCD with a pixel size of 13 μ m (H) × 13 μ m (V), maximum data output frequency of 20MHz, dynamic range of 1600:1, unidirectional, single ended output, series selection and blue light response enhancement function. Il-e2 TDI-CCD can be divided into three functional areas, namely photosensitive element detection area, charge transfer area and detection output area.
2.3 timing analysis of il-e2 TDI-CCD
The driving timing control of TDI-CCD is more complex than that of ordinary linear CCD. The timing control of il-e2 TDI-CCD includes various DC level control and clock pulse sequence control. For the former, it mainly includes supply voltage VDD, output gate voltage vest, overflow gate voltage VOV, substrate voltage VBB and series control bias voltage; for the latter, it mainly includes row transfer clock pulse TCK, pixel shift read-out clock pulse CR1 and CR2, output reset clock pulse rst, TDI direction shift register driving clock pulse ci1-ci4, series control clock pulse css6, CS S12、CSS24、CSS48。 When TDI-CCD works, when the line transfer clock pulse TCK is high level, the signal charge generated by pixel photosensitivity is accumulated and transferred to the output shift register along the TDI direction (TDI series is controlled by TDI series and selected as one of 6, 12, 24, 48, 96) under the joint action of TDI direction shift register driving clock pulses ci1, ci2, Ci3, ci4; when TCK is low level, the signal charge generated by pixel photosensitivity is accumulated and transferred to the output shift register, Under the action of pixel shift readout clock pulses CR1 and CR2, TDI-CCD outputs reset clock pulse rst. At every high level of effective level, the output signal of TDI-CCD outputs a signal until the signal is output. After that, TCK changes from low level to high level, and ci1, ci2, Ci3, ci4 also change to effective level, transferring the signal charge generated by pixel photosensitization after the last transfer, and starting a new cycle. The detailed correspondence of these timing controls is shown in Figure 2.
For this TDI-CCD timing design and ordinary linear array CCD timing design has the following outstanding characteristics. (1) In TDI direction, there are 4-phase shift registers driving clock, their cycle is consistent with row cycle, high-level pulse width T3 should be greater than 3 μ s, the rising edge of ci1 lags behind the rising edge of TCK, the falling edge of ci2 lags behind the falling edge of TCK, and the high-level pulse width of ci1 and ci2 has at least 1 μ s overlap. Ci3 and ci4 are the phase inversion of ci1 and ci2 respectively. (2) This TDI-CCD can work at 96, 48, 24, 12 and 6 levels by css6, css12, css24 and css48.
The principle and working process analysis of 3 timing generator
The timing generator generates all kinds of clock pulse signals needed by TDI-CCD, video processor and image data output. The timing generator plays a role of time synchronization and coordination in the work of CCD imaging unit. It is controlled by the instructions and parameters given by the sequential controller. The timing controller controls the line transfer period, integral series, control instructions and parameters to the timing controller in the form of serial data. The timing generator generates the clock pulse signals required by TDI-CCD and video processor according to the instructions and data given by the timing controller Line transfer clock pulse, pixel shift readout clock pulse, output reset clock pulse, TDI direction shift register drive clock pulse, series control clock pulse, correlation double sampling clock pulse, a / D converter sampling clock pulse, etc. In order to improve the reliability of operation, when the control instructions and parameters in the sequence controller are not updated, the sequence generator will work according to the initial set parameters in the sequence controller.
Design of timing generator: timing generator generates all kinds of timing needed by TDI-CCD, video processor and image data output. All the time sequences are generated by the logic and combination operation of the main oscillator pulse sequence through the step-by-step frequency division pulse sequence. The strict phase relationship between them is the basis of camera system coordination. The function block diagram of timing generator is shown in Figure 3. As soon as the camera system is powered on, it should work in the internal default mode immediately, so that it can judge whether the system is normal or not. If the external or internal setting command is invalid, the system will return to the default mode, which is a reflection of the reliability of the camera system. All kinds of clocks generated by timing generator are completed by VHDL language.
Realization of timing generator for scientific CCD camera with FPGA
4.1 FPGA technology and FPGA devices
FPGA field programmable gate array (fpga-fpga) is a programmable logic device technology developed rapidly in recent years. This kind of chip based on EDA technology is becoming the mainstream of electronic system design. Large scale programmable logic device FPGA is the most widely used programmable ASIC. Designers can use it to design ASIC in office or laboratory, which can greatly shorten the time to market and reduce the development cost. In addition, FPGA also has the characteristics of static repetitive programming and dynamic reconfiguration in the system, so that the functions of hardware can be modified by programming like software. Therefore, the application prospect of FPGA technology is very broad.
Xc2vp20-ff1152 is a virtex II Pro Series FPGA produced by Xilinx company. It has rich internal resources, including 8 digital clock managers (DCM), 290kbits distributed ram, 88 × 16kbyte block ram, 88 18 × 18 dedicated multipliers, 2 powerpc405 cores, 564 configurable I / O pins (276 at most) For differential I / O, the speed is as high as 3.125gbps), and the maximum internal operating frequency is 420MHz.
4.2 design and Simulation of timing generator for scientific CCD camera based on FPGA
The pixel number of il-e2 TDI-CCD has three kinds: 5121024 and 2048 per line. This paper takes 2048 pixel number as an example to design timing circuit. 2048 is the effective number of pixels. Since there are 5 isolated pixels and 4 dark reference pixels in each row, the design should ensure that at least 2057 pixels are output per line, that is to say, there are at least 2057 CR1, CR2 and RST driving pulses in each row cycle. In addition to 2057 pixel driving pulses per line, the rest are empty driving pulses. The more the pulse number of the air drive artery, the longer the line cycle time, the longer the CCD exposure integration time, and the corresponding improvement of sensitivity. However, too long exposure integration time will make the CCD output saturated distortion, so the number of air driving pulses is not easy to be too much. Integration time and pixel shift readout clock frequency are the design basis of CCD timing circuit. In the engineering application, we calculate the travel integral time (T) as 0.365ms according to the technical index requirements, so as to determine the appropriate system master clock. The driving sequence is written in VHDL. The program mainly includes: (1) calling the required library functions and packages; (2) defining the input and output ports; (3) dividing the input system clock by a counter. (4) Generation and output of driving timing signal. The timing design of xc2vp20-ff1152 device is carried out by the design software ise6.2 of Xilinx company. All the above functions are verified by timing simulation and engineering application. The time sequence simulation waveform of system logic function is shown in Fig. 4.
The innovation of this paper is to use FPGA device to design scientific CCD camera timing generator, which makes the circuit from the original complex design to only use one piece of Xilinx company’s programmable device xc2vp20-ff1152. The results of independent unit test and system debugging show that the circuit of CCD camera timing generator based on FPGA technology can simplify the circuit and improve the integration of the system. The anti-interference ability of the timing generator is also enhanced, and its power consumption is also reduced. Thus, the scientific CCD is realized At the same time, the design and debugging cycle of the camera is greatly shortened. The design scheme opens up a wider prospect for the application of TDI-CCD in scientific CCD camera.
Editor in charge: GT