By del Jones
Data intensive applications in many industries continue to break through the boundaries and need to transmit payload data quickly and efficiently. 5g communication network system requires more bandwidth of infrastructure and its connectors. In the aerospace and defense industry, this is equivalent to radar applications and complex data analysis instruments to process more information in a shorter time. Accordingly, the rapid growth of high bandwidth testing and analysis means the need to use faster, larger capacity of electronic test equipment.
With the increasing demand for data, JEDEC Solid State Technology Association needs to introduce a new jesd204 standard to realize the high-speed serial link between data converters and logic devices. Version b of the standard was released in 2011, and the serial link data rate was increased to 12.5gbps, which ensured a deterministic delay from one power supply cycle to the next, and met the higher bandwidth requirements of converter based applications at that time. The latest version of the standard, jesd204c, was released at the end of 2017 to continue to support the rising trend of performance requirements for current and next generation multi Gigabit data processing systems. Jesd204c sub committee has set four high-level goals for the new revised version of the standard: to improve the channel rate to support higher bandwidth applications, to improve the efficiency of payload transmission, and to improve link robustness. In addition, they hope to write a clearer specification than jesd204b and fix some errors in this version of the standard. They also want to offer the option of backward compatibility with jesd204b. The complete jesd204c specification can be obtained through JEDEC.
This introductory article consists of two parts. It aims to introduce the jesd204c standard, highlight the differences between jesd204b and jesd204c, and elaborate the key new features introduced to achieve the above goals, provide a more user-friendly interface, and meet the bandwidth capacity requirements of all walks of life. The first part of this series outlines version differences and new features, and the second part delves into the most important new features.
Summary of jesd204c changes
Jesd204c specification improves readability and clarity through reasonable chapter structure, including five main parts. The “Introduction and general requirements” section covers the requirements applicable to all layers of the implementation plan. The part for physical, transmission and data link layers (8B / 10B, 64b / 66b and 64b / 80B) covers the requirements specifically applicable to these layers of the implementation scheme. Several new terms are introduced in the standard, which are mainly related to the new 64b / 66b and 64b / 80B link layers and the new synchronization process of these link layers. Although the transport layer is the same as jesd204b, the physical layer has changed a lot. These changes, subtle changes in clock and synchronization, and the increase in FEC are summarized in the following sections.
Jesd204c introduces several new terms and configuration parameters to describe the functions related to 64b / 66b and 64b / 80B link layers. Table 1 lists some of the most relevant terms and parameters, as well as a brief description of each term and parameter. This will be further explained in the following sections.
Table 1. New terms and parameters
|block||A structure that starts with a 2-bit synchronous header and contains a total of 66 or 80 (BKW) bits|
|BkW||Block width; the number of digits in a block|
|CMD||Command, related to command channel|
|Command channel||A data stream that uses the extra bandwidth provided by the synchronization header|
|E||The number of blocks in an extended block|
|EMB_ LOCK||A state in which an extension block is declared to be aligned|
|EoEMB||Extended multi block end identifier|
|EoMB||Multi block end identification sequence (00001); also known as pilot signal|
|Extended multi block||A set of data containing one or more blocks|
|FEC||Forward error correction|
|Fill bit||An artificial fill bit for expanding block size in 64b / 80B encoding mode|
|LEMC||Local extended multi block clock|
|Multi block||A set of data containing 32 blocks|
|PCS||Physical coding sublayer|
|SH_ LOCK||A state d that states that the synchronization header is aligned|
|Synchronization header||The first two data bits of a block should be changed|
Jesd204c has the same transport layer as jesd204b. The data frames assembled in the transport layer are sent through the link in the form of eight octets. The chapter structure, text and pictures of this part of the standard have been changed to improve the clarity.
Due to some characteristics of 64 bit coding scheme, in some configurations, the frame boundary may not be aligned with the block boundary (the frame may not exactly contain eight octets). Details and their implications will be explained in the second part of this series.
data link layer
As mentioned earlier, the standard has two main parts covering different data link layer schemes. The 8B / 10B coding scheme in the previous version of jesd204 standard, including using sync ~ pin and K.28 character for synchronization, channel alignment and error monitoring, remains unchanged as backward compatibility options. But in the long run, most applications may use one of the new 64 bit coding schemes in jesd204c. The 64b / 66b coding scheme based on IEEE802.3 can provide the highest efficiency. Although it is called coding scheme, there is no coding (such as 8B / 10B coding). In this scheme, only two header bits are added before 64 bit payload data. Because of this situation, scrambling must be carried out to maintain DC balance and ensure sufficient data changes, so that the clock and data recovery (CDR) circuit in jesd204c receiver can reliably recover the clock. This is explained in more detail in the second part of this series. In addition, the 64b / 80B option is added, which has the same clock ratio as the 8B / 10B scheme, and allows the use of new features such as forward error correction. The two 64 bit coding schemes are not compatible with the 8B / 10B coding used in jesd204b.
Jesd204c has increased the upper limit of channel rate to 32gbps, while the lower limit of 312.5mbps determined in earlier versions remains unchanged. The upper limit of jesd204b is 12.5gbps. Although it is not strictly prohibited, 8B / 10B coding is not recommended for channel rates above 16gbps, and 64b coding is not recommended for channel rates below 6gbps.
Jesd204c introduces two categories to define the characteristics of physical interfaces. Table 2 lists the channel rates associated with each class. Table 3 lists the channel types in class C and the associated weighting and equalization characteristics.
T Table 2. Channel data rate corresponding to data interface class
|Data interface class||Minimum data rate (Gbps)||Maximum data rate (Gbps)|
|B-3||zero point three one two five||three point one two five|
|B-6||zero point three one two five||six point three seven five|
|B-12||six point three seven five||twelve point five|
|C||six point three seven five||Thirty-two|
Table 3. Jesd204c32gbps interface device class characteristics
|class||Relative power||Transmitter FFE (minimum)||Receiver CTLE (minimum)||Receiver DFE tap (minimum)|
Jesd204c also introduces the concept of jesd204 channel working margin (jcom), which is used to confirm whether it meets the class C physical layer standard. This work margin calculation is a supplement to the eye pattern template that applies the class B physical layer implementation scheme (described in this version and previous revisions of the standard).
Clock and synchronization
Jesd204c will retain the sysref and device clock defined in jesd204b. However, when using any 64 bit coding scheme, sysref is not used to align LMFC, but to align local extended multi block clock (lemc) to provide a mechanism for deterministic delay and multi chip synchronization.
The synchronization process of 64 bit coding scheme is completely different from that used in jesd204b. The sync signal has been removed, and the synchronization initialization and error report will now be processed in the application layer software. Therefore, there is no code group synchronization (CGS) or initial channel alignment sequence (ILAS) in the new version. Synchronization header synchronization, extended multi block synchronization and extended multi block alignment are new terms used to describe synchronization process. Each of these synchronization phases is implemented using a 32-bit synchronization word. This is discussed in detail in the second part of this series.
Please note that for 8B / 10B encoding, both the sync pin and ILAS are reserved.
Deterministic delay and multi chip synchronization
As mentioned above, the mechanisms for deterministic delay and multi chip synchronization are mostly the same as jesd204b. When one of the 64 bit coding schemes is used, there is no subclass 2 option and only subclass 1 operation is supported. Sysref signal is used to align lemcs of all devices in jesd204 subsystem.
Forward error correction
To achieve the goal of providing more robust links at higher channel rates, jesd204c includes FEC option. The algorithm is based on the firecode, which may be particularly useful for instrument applications. This is an optional feature and can only be used when one of the 64 bit encoding schemes is used.
Farr code is a cyclic code to correct single burst error. The advantage of cyclic codes is that their codewords can be expressed as polynomials over finite fields instead of vectors. The frame used in Farr code can be divided into two parts to support faster decoding.
The second part of the jesd204c introduction series is coming soon. We will explore the key elements of the jesd204c standard, which form the problem-solving technology we described in the opening. Specifically, we will take a closer look at the bandwidth efficiency improvement achieved by the 64b / 66b coding scheme and the 32gbps physical layer specification for increasing bandwidth. We will also take an in-depth look at the new synchronization process and the optional forward error correction aspects of the standard to improve link robustness.
For more information about jesd204 and its implementation in ADI products, please visit the jesd204 serial interface page of ADI company.