The circuit shown in Figure 1 is a simplified diagram of a 14 bit, 125 MSPs four channel ADC system. The circuit uses back-end digital summation to improve the signal-to-noise ratio (SNR) from 74 dBfs of a single channel ADC to 78.5 dBfs of a four channel ADC. This technology is especially suitable for applications requiring high SNR (such as ultrasound and radar), and uses modern high-performance, low-power, four channel pipelined ADC.

The circuit uses the basic principle that the uncorrelated noise source is added on the basis of square sum root (RSS) and the signal voltage is added on the basis of linearity. Figure 1. Basic block diagram of summing four parallel ADCs to obtain higher SNR

Circuit description

The input of each ADC consists of a signal term (VS) and a noise term (VN). The total voltage Vt can be obtained by summing the four noise voltage sources, which is the linear sum of four signal voltages plus four noise voltage squares and roots, for example: Since VS1 = VS2 = vs3 = VS4, the signal can be effectively multiplied by 4, while the converter noise – with an equivalent RMS value – is only multiplied by 2, the signal-to-noise ratio increases by a factor of 2, i.e. 6.02 dB. Therefore, the SNR increment of 6.02 DB is the result of an additional effective resolution bit caused by the sum of four similar signals. Since SNR (DB) = 6.02n + 1.76 dB, where n is the number of digits, so Table 1 shows the theoretical SNR values obtained by summing multiple ADC outputs. For convenience, it is obvious that you should choose to sum the four ADCs. Some critical situations may require more ADC summation, but it depends on other system specifications (including cost) and available board space.

Table 1. Relationship between increasing SNR and ADC number SNR increment of ADC number (DB) The ideal SNR for a 14 bit ADC is (6.02 & times; 14) + 1.76 = 86.04 dB. The typical SNR specified in the ad9253 data book is 74 dB, but the resulting ENOB is 12 bits. The circuit shown in Figure 1 integrates the front end of the passive receiver, which is composed of four analog input channels. The device is a 14 bit, 125 MSPs four channel analog-to-digital converter ad9253.

The circuit accepts a single ended input and converts the input into a differential signal through two broadband (3GHz) m / A-COM etc1-1-13 baluns with an impedance ratio of 1:1 in a double balanced configuration, as shown in Figure 2. Figure 2. Input analog summation network

All four ADC inputs are connected on the secondary side of the balun configuration. There is no gain in the circuit, and each analog input pair has a simple filtering function to reduce the residual recoil signal that may be fed back to the adjacent ADC channel.

Tagged: