In recent years, most of speech recognition research focuses on algorithm design and improvement. With the rapid development of semiconductor technology, the increasing scale of integrated circuits and the continuous improvement of various R & D technology levels, the introduction of new hardware platform, speech recognition implementation platform has more choices. After combining with embedded system based on DSP, FPGA, ASIC and other devices, speech recognition technology is gradually developing towards practicality and miniaturization. Based on the research of the existing speech feature parameters and isolated word speech recognition model, this paper focuses on the application of DTW model based on dynamic time warping algorithm in the field of isolated word speech recognition. Combined with SOPC system based on FPGA, the isolated word speech recognition system with better accuracy and speed is implemented on the embedded platform.

  Design of 24 bit audio codec

De2 board provides high quality 24 bit Wolfson wm8731 audio codec chip. The chip supports three ports of microphone input, line in and line out, and can adjust the sampling frequency from 8kHz to 96KHz. The chip development board manufacturer has fixed serial I2C bus protocol to transmit data, and the corresponding port has been fixed in cyclone II 2c35 FPGA. The circuit diagram is shown in Figure 19.

Circuit design of speech recognition system based on FPGA

The hardware connection of the system is fixed. The design only needs to set the control word according to the working mode of the chip, and write the program according to the sequence diagram of the chip. The data source of the system is collected from this circuit, so we must be familiar with the use of wm8731. The specific implementation of the system acquisition part will be described in detail in Chapter 5.

  LCD display module

Most of the information exchanged between human and computer is completed through the prompt information of LCD. This module uses the character display module cfah1702b-tmc-jp, which has two lines of 16 character display, 5V power supply, 8-bit register control word, including instruction register (IR) and data register (DR). It has 8-bit data bus d0-d7, three control ports of RS, R / W and en, and has character contrast adjustment and backlight. It can find corresponding numbers or English characters through character storage. The figure below is the schematic diagram of LCD on de2 board.

Circuit design of speech recognition system based on FPGA

The overall design of the system is based on de2 development platform, using SOPC technology based on Nios II. The advantage of this solution is that the system on chip is realized and the physical volume and overall power consumption of the system are reduced; At the same time, the control core of the system is implemented in FPGA, which makes it very convenient to update and upgrade the system, and greatly improves the versatility and maintainability of the system. In addition, because the system needs a lot of high-speed data operation, the author makes full use of the rich hardware multiplier of cyclone II chip in the design, and realizes the endpoint detection module of speech signal, FFT fast Fourier transform module, DCT discrete cosine transform module and other hardware design modules. In order to improve the overall performance of the system, the author makes full use of the high-speed parallel advantage of FPGA and the Avalon bus custom hardware peripherals in the supporting development environment, which greatly improves the ability of the system to process digital signals, and its performance is better than that of traditional microcontrollers and ordinary DSP chips.

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