The ultimate purpose of speaker independent speech recognition technology research is to enable computers and other devices to “understand” human speech, extract the specific information contained in speech, and become the most convenient means of human-computer communication and interaction. Because the speech signal itself has uncertainty, dynamics and continuity, it brings great difficulties to accurately quantify and process the signal. Each person’s speech needs to establish different speech samples, which also brings bottleneck constraints to the popularization of recognition. At present, speech recognition is to establish a feature library first, and then compare the signal to be recognized with the feature library to obtain similar results and determine the output. In essence, it belongs to the basic theory based on statistical pattern, which is composed and implemented in two stages: language model training and recognition analysis.
Overall structure of system design
The system takes stm32f103c8t6 microcontroller as the control core, combined with the minimum core circuit of microcontroller, ld3320 speech recognition circuit, SD card circuit, power supply circuit, user key input circuit, serial port data output circuit, status indication circuit, etc. The system is small in size and can be integrated into the user’s circuit or board as an embedded component unit. After power on, stm32f108c8t6 internal program carries out program initialization, SD card file system initialization, ld3320 initialization, and then waits for recognition audio reception. After recognition, output response information or decode audio. The overall structure of the system is shown in Figure 2, Finally, all functions of building block functional components are realized.
Micro control core circuit
The system uses the arm cortex m3 core and the 32-bit high-performance single chip microcomputer stm32f103c8t6 of ST company as the control core. The chip can reach the working frequency of 72 MHz, has built-in high-speed memory (64 kb flash memory and 20 KB SRAM), has rich I / O port resources and peripherals linked to two APB buses. It includes 12b ADC, general 16b timer, I2C, SPI, USART, USB, can and other bus or serial communication interfaces. The on-chip resources and expansion interfaces are very rich. The micro control core is specially designed for embedded product applications with high stability, low power consumption, real-time performance and high performance price ratio. The core chip can meet the functional requirements of speaker independent speech recognition. The minimum system of stm32f103c8t6 is composed of relevant circuits. The hardware PCB also integrates functional pin output interface, SD card interface, USB Download / debugging circuit, user keys, power supply circuit, etc. the circuit diagram of the core system is shown in Figure 3, which meets the functional requirements with other peripheral extensions.